Less expensive test pattern generation technique

A new source of computational saving for test pattern generation (i.e. information reusing) is presented. Combined with a fault simulator based on the critical path tracing method, the proposed technique can make full use of the test pattern information generated from last pattern to derive a set of new tests by means of critical path transitions. Based on this technique, fault propagation procedure is no longer required in the subsequent pattern generation process. The technique also leads to a simplified line justification procedure. Sufficient conditions for critical path transitions are given to guarantee the effectiveness of the newly derived tests and the correctness of such transitions. Experiments using the ISCAS-85 benchmark circuits show that, when the technique is used with a deterministic test pattern generation algorithm (DTPG), computational cost is greatly reduced without a substantial increase in test length.