Implementation and Analysis of a 15-Level Inverter Topology with Reduced Switch Count

Mohammad Fahad; Marif Daula Siddique; Atif Iqbal; Adil Sarwar; Saad Mekhilef

doi:10.1109/ACCESS.2021.3064982

Implementation and Analysis of a 15-Level Inverter Topology with Reduced Switch Count

Mohammad Fahad
, Marif Daula Siddique^*
, Atif Iqbal
, Adil Sarwar
, Saad Mekhilef

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

40 Scopus citations

Abstract

Multilevel inverters remain an area of research interest due to the superior performance against a two-level counterpart. Reducing the switch count and stress on the power electronic switches while maintaining a sinusoidal stepped output remains a challenge. A multilevel inverter topology has been proposed in this work which utilizes twelve switches and four dc voltage sources to produce a 15-level staircase output voltage waveform. The objective is to reduce the harmonic in the output voltage and thereby reducing the cost of filter requirement and maintaining high efficiency throughout the operating range. Control of output voltage has been done using the Nearest Level Pulse Width Modulation Strategy (NLPWM). Simulation and hardware implementation of the topology under different loads and dynamic conditions are presented to validate the robust performance.

Original language	English
Article number	9373402
Pages (from-to)	40623-40634
Number of pages	12
Journal	IEEE Access
Volume	9
DOIs	https://doi.org/10.1109/ACCESS.2021.3064982
State	Published - 2021
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 2013 IEEE.

Keywords

Multilevel inverters
nearest level control (NLC)
power converters
total harmonic distortion (THD)

ASJC Scopus subject areas

General Computer Science
General Materials Science
General Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ACCESS.2021.3064982

Cite this

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title = "Implementation and Analysis of a 15-Level Inverter Topology with Reduced Switch Count",

abstract = "Multilevel inverters remain an area of research interest due to the superior performance against a two-level counterpart. Reducing the switch count and stress on the power electronic switches while maintaining a sinusoidal stepped output remains a challenge. A multilevel inverter topology has been proposed in this work which utilizes twelve switches and four dc voltage sources to produce a 15-level staircase output voltage waveform. The objective is to reduce the harmonic in the output voltage and thereby reducing the cost of filter requirement and maintaining high efficiency throughout the operating range. Control of output voltage has been done using the Nearest Level Pulse Width Modulation Strategy (NLPWM). Simulation and hardware implementation of the topology under different loads and dynamic conditions are presented to validate the robust performance.",

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year = "2021",

doi = "10.1109/ACCESS.2021.3064982",

language = "English",

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pages = "40623--40634",

journal = "IEEE Access",

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T1 - Implementation and Analysis of a 15-Level Inverter Topology with Reduced Switch Count

AU - Fahad, Mohammad

AU - Siddique, Marif Daula

AU - Iqbal, Atif

AU - Sarwar, Adil

AU - Mekhilef, Saad

PY - 2021

Y1 - 2021

N2 - Multilevel inverters remain an area of research interest due to the superior performance against a two-level counterpart. Reducing the switch count and stress on the power electronic switches while maintaining a sinusoidal stepped output remains a challenge. A multilevel inverter topology has been proposed in this work which utilizes twelve switches and four dc voltage sources to produce a 15-level staircase output voltage waveform. The objective is to reduce the harmonic in the output voltage and thereby reducing the cost of filter requirement and maintaining high efficiency throughout the operating range. Control of output voltage has been done using the Nearest Level Pulse Width Modulation Strategy (NLPWM). Simulation and hardware implementation of the topology under different loads and dynamic conditions are presented to validate the robust performance.

AB - Multilevel inverters remain an area of research interest due to the superior performance against a two-level counterpart. Reducing the switch count and stress on the power electronic switches while maintaining a sinusoidal stepped output remains a challenge. A multilevel inverter topology has been proposed in this work which utilizes twelve switches and four dc voltage sources to produce a 15-level staircase output voltage waveform. The objective is to reduce the harmonic in the output voltage and thereby reducing the cost of filter requirement and maintaining high efficiency throughout the operating range. Control of output voltage has been done using the Nearest Level Pulse Width Modulation Strategy (NLPWM). Simulation and hardware implementation of the topology under different loads and dynamic conditions are presented to validate the robust performance.

KW - Multilevel inverters

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KW - total harmonic distortion (THD)

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ER -

Implementation and Analysis of a 15-Level Inverter Topology with Reduced Switch Count

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

UN SDGs

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