IMPACT OF VLSI TECHNOLOGY ON THE HARDWARE DESIGN LANGUAGE AHPL.

Z. Navabi; M. Masud; W. J. Knapp; F. J. Hill

IMPACT OF VLSI TECHNOLOGY ON THE HARDWARE DESIGN LANGUAGE AHPL.

Z. Navabi^*
, M. Masud
, W. J. Knapp
, F. J. Hill

^*Corresponding author for this work

King Fahd University of Petroleum & Minerals

Research output: Contribution to journal › Conference article › peer-review

Abstract

The ongoing development of a new three stage multiple application compiler for AHPL is described. The first two compiler stages are application independent with distinct third stages developed as required. The emphasis is on the VLSI realization of AHPL source descriptions in terms of sequential logic arrays.

Original language	English
Pages (from-to)	912-915
Number of pages	4
Journal	Journal de physique Paris
Volume	2
State	Published - 1980

ASJC Scopus subject areas

General Engineering

Cite this

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title = "IMPACT OF VLSI TECHNOLOGY ON THE HARDWARE DESIGN LANGUAGE AHPL.",

abstract = "The ongoing development of a new three stage multiple application compiler for AHPL is described. The first two compiler stages are application independent with distinct third stages developed as required. The emphasis is on the VLSI realization of AHPL source descriptions in terms of sequential logic arrays.",

author = "Z. Navabi and M. Masud and Knapp, \{W. J.\} and Hill, \{F. J.\}",

year = "1980",

language = "English",

volume = "2",

pages = "912--915",

journal = "Journal de physique Paris",

issn = "0302-0738",

publisher = "Societe Francaise De Physique",

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TY - JOUR

T1 - IMPACT OF VLSI TECHNOLOGY ON THE HARDWARE DESIGN LANGUAGE AHPL.

AU - Navabi, Z.

AU - Masud, M.

AU - Knapp, W. J.

AU - Hill, F. J.

PY - 1980

Y1 - 1980

N2 - The ongoing development of a new three stage multiple application compiler for AHPL is described. The first two compiler stages are application independent with distinct third stages developed as required. The emphasis is on the VLSI realization of AHPL source descriptions in terms of sequential logic arrays.

AB - The ongoing development of a new three stage multiple application compiler for AHPL is described. The first two compiler stages are application independent with distinct third stages developed as required. The emphasis is on the VLSI realization of AHPL source descriptions in terms of sequential logic arrays.

UR - https://www.scopus.com/pages/publications/0019263304

M3 - Conference article

AN - SCOPUS:0019263304

SN - 0302-0738

VL - 2

SP - 912

EP - 915

JO - Journal de physique Paris

JF - Journal de physique Paris

ER -

IMPACT OF VLSI TECHNOLOGY ON THE HARDWARE DESIGN LANGUAGE AHPL.

Abstract

ASJC Scopus subject areas

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