Abstract
This study proposes a low complex and high efficient dual-reference voltage-based pulse width modulation (DRV-PWM) scheme for three-phase five-level hybrid active neutral-point-clamped (HANPC) inverters. Although phase-shifted carrier PWM (PSC-PWM) is capable of naturally balancing dc-link and flying capacitors voltages, such a process requires a tedious and sophisticated adjustment of the phase-shift between the PWM signals, particularly in a digital signal processor (DSP). As a result, a phase-delay eventually occurs, which leads to unevenly distributed thermal losses among the three phases of the five-level HANPC inverter. Therefore, this study introduces an alternative switching scheme that has the same merits as the conventional PSC-PWM in naturally balancing the voltages without requiring voltage sensors. It also balances the thermal losses across the three phases, which enhances the reliability and efficiency of the switching devices. The proposed DRV-PWM is experimentally evaluated in comparison to conventional PSC-PWM on a TMS320F28377S DSP. The experimental results reveal that the proposed DRV-PWM effectively synchronizes the execution of the three-phase pole voltages while also keeping the thermal losses evenly distributed among the three phases.
| Original language | English |
|---|---|
| Pages (from-to) | 3047-3057 |
| Number of pages | 11 |
| Journal | Journal of Electrical Engineering and Technology |
| Volume | 19 |
| Issue number | 5 |
| DOIs | |
| State | Published - Jul 2024 |
| Externally published | Yes |
Bibliographical note
Publisher Copyright:© The Author(s) under exclusive licence to The Korean Institute of Electrical Engineers 2023.
Keywords
- Digital signal processor (DSP)
- Dual-reference voltage
- Five-level hybrid active neutral-point-clamped (HANPC) inverters
- Phase shifted carrier pulse width modulation (PSC-PWM)
- Thermal losses balancing
- Time-delay
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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