High defect tolerant low cost memory chips

Costas Argyrides; Ahmad Al-Yamani; Dhiraj K. Pradhan

doi:10.1109/SOCC.2007.4545440

High defect tolerant low cost memory chips

Costas Argyrides^*, Ahmad Al-Yamani, Dhiraj K. Pradhan

^*Corresponding author for this work

King Fahd University of Petroleum & Minerals

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Memories are among the most dense integrated circuits fabricated, and so, have the highest rate of defects. This paper proposes a scheme for selecting the right redundancy in memory designs driven by the fabrication cost and the yield. It also proposes a new memory architecture that fills the gap between the existing all-or-none extremes with memories. Experiments show that the new scheme reduces cost by up to 70%.

Original language	English
Title of host publication	Proceedings - 20th Anniversary IEEE International SOC Conference
Pages	119-122
Number of pages	4
DOIs	https://doi.org/10.1109/SOCC.2007.4545440
State	Published - 2007

Publication series

Name	Proceedings - 20th Anniversary IEEE International SOC Conference

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/SOCC.2007.4545440

Cite this

@inproceedings{dd23d536a0114a5c899b01ddd3d0a8db,

title = "High defect tolerant low cost memory chips",

abstract = "Memories are among the most dense integrated circuits fabricated, and so, have the highest rate of defects. This paper proposes a scheme for selecting the right redundancy in memory designs driven by the fabrication cost and the yield. It also proposes a new memory architecture that fills the gap between the existing all-or-none extremes with memories. Experiments show that the new scheme reduces cost by up to 70\%.",

author = "Costas Argyrides and Ahmad Al-Yamani and Pradhan, \{Dhiraj K.\}",

year = "2007",

doi = "10.1109/SOCC.2007.4545440",

language = "English",

isbn = "9781424415922",

series = "Proceedings - 20th Anniversary IEEE International SOC Conference",

pages = "119--122",

booktitle = "Proceedings - 20th Anniversary IEEE International SOC Conference",

}

TY - GEN

T1 - High defect tolerant low cost memory chips

AU - Argyrides, Costas

AU - Al-Yamani, Ahmad

AU - Pradhan, Dhiraj K.

PY - 2007

Y1 - 2007

N2 - Memories are among the most dense integrated circuits fabricated, and so, have the highest rate of defects. This paper proposes a scheme for selecting the right redundancy in memory designs driven by the fabrication cost and the yield. It also proposes a new memory architecture that fills the gap between the existing all-or-none extremes with memories. Experiments show that the new scheme reduces cost by up to 70%.

AB - Memories are among the most dense integrated circuits fabricated, and so, have the highest rate of defects. This paper proposes a scheme for selecting the right redundancy in memory designs driven by the fabrication cost and the yield. It also proposes a new memory architecture that fills the gap between the existing all-or-none extremes with memories. Experiments show that the new scheme reduces cost by up to 70%.

UR - https://www.scopus.com/pages/publications/51049098683

U2 - 10.1109/SOCC.2007.4545440

DO - 10.1109/SOCC.2007.4545440

M3 - Conference contribution

AN - SCOPUS:51049098683

SN - 9781424415922

T3 - Proceedings - 20th Anniversary IEEE International SOC Conference

SP - 119

EP - 122

BT - Proceedings - 20th Anniversary IEEE International SOC Conference

ER -

High defect tolerant low cost memory chips

Abstract

Publication series

ASJC Scopus subject areas

Access to Document

Fingerprint

Cite this