Hardware implementation of a parallel noise clearing algorithm

M. Atiquzzaman

doi:10.1016/0165-6074(89)90263-9

Hardware implementation of a parallel noise clearing algorithm

M. Atiquzzaman^*

^*Corresponding author for this work

King Fahd University of Petroleum & Minerals

Research output: Contribution to journal › Article › peer-review

Abstract

Dedicated hardware can be used to release the CPU of an image processing system, of routine image pre-processing tasks, thereby speeding up the operational speed of the system. This paper describes the hardware implementation of a one-pass fill, shrink and expand algorithm to clear random noise from an image. The three operations, comprising the algorithm, operate in parallel on a raster-scan image in a pipelined system. Simulation results are given, and the operating speed and cost are compared with those of a multiprocessor system using 8086.

Original language	English
Pages (from-to)	119-128
Number of pages	10
Journal	Microprocessing and Microprogramming
Volume	26
Issue number	2
DOIs	https://doi.org/10.1016/0165-6074(89)90263-9
State	Published - Jun 1989

Keywords

2-D convolution
Fill-shrink-and-expand
Hardware implementation
Image filtering
Image processing
Noise removal
Performance evaluation

ASJC Scopus subject areas

General Engineering

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10.1016/0165-6074(89)90263-9

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abstract = "Dedicated hardware can be used to release the CPU of an image processing system, of routine image pre-processing tasks, thereby speeding up the operational speed of the system. This paper describes the hardware implementation of a one-pass fill, shrink and expand algorithm to clear random noise from an image. The three operations, comprising the algorithm, operate in parallel on a raster-scan image in a pipelined system. Simulation results are given, and the operating speed and cost are compared with those of a multiprocessor system using 8086.",

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AB - Dedicated hardware can be used to release the CPU of an image processing system, of routine image pre-processing tasks, thereby speeding up the operational speed of the system. This paper describes the hardware implementation of a one-pass fill, shrink and expand algorithm to clear random noise from an image. The three operations, comprising the algorithm, operate in parallel on a raster-scan image in a pipelined system. Simulation results are given, and the operating speed and cost are compared with those of a multiprocessor system using 8086.

KW - 2-D convolution

KW - Fill-shrink-and-expand

KW - Hardware implementation

KW - Image filtering

KW - Image processing

KW - Noise removal

KW - Performance evaluation

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IS - 2

ER -

Hardware implementation of a parallel noise clearing algorithm

Abstract

Keywords

ASJC Scopus subject areas

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