Hardware implementation of a configurable and power-efficient current conveyor architecture

This paper presents a configurable and power-efficient modified second-generation current conveyor (M-CCII) architecture. A self-biased Miller-compensated transconductance amplifier (OTA) and arrays of class AB amplifiers construct the architecture. Hence, it can be configured and quickly synthesized for various applications. Furthermore, the stability performance of the proposed architecture is assessed using the signal flow graph (SFG) based on the driving point impedance (DPI) approach. The suggested architecture is designed and simulated with a 1.8 V power supply in TSMC 180 nm CMOS technology. It consumes a relatively low power of 2.46 μW and occupies a silicon area of 33 μm x 125 μm. The proposed M-CCII architecture is configured to provide a current gain of 14 dB with a bandwidth of 3.16 MHz and a voltage gain of -0.22 dBm with a bandwidth of 3 MHz. A low input resistance of 25 Ω and a high output resistance of up to 41 MΩ are achieved. The configured architecture can deliver a current range of up to ±7.6 μA and operate within an input voltage range of 1.22 V with a total harmonic distortion of 2%. The integrated input referred noise reaches 14.6 pA within a bandwidth of 10 Hz. Monte Carlo simulations and process-voltage-temperature variation analysis have been employed to ensure robust and reliable performance across manufacturing variations. Commercial integrated circuits like LMC6482, ALD11007, and ALD11006 are used to experimentally confirm the reconfigurability and reusability of the suggested M-CCII design. The experiment results demonstrate that the proposed architecture can be used in a range of analog signal-processing applications.