Hardware design and VLSI implementation of a byte-wise crc generator chip

In this paper the hardware design and VLSI implementation of a byte-wise CRC generator is presented. The algorithm is based on the work presented in [10] in which a software implementation was proposed. The byte-wise CRC algorithm is translated to hardware and expressed in AHPL [6]. The method used here calculates CRC on the fly and is much faster than the look-up table method proposed by Lee [5]. The chip is 8 times faster than the serial implementation of [12] with smaller hardware requirements (occupies lesser area). The number of clock cycles required to generate and transmit any CRC (for an 8 byte message) is just two more than the time required to calculate it (in all 10 clock pulses). The CRC chip can be used in a number of applications. These include areas such as error detection and correction in data communications, signature analysis, and mass storage devices for parallel information transfers.