Abstract
This paper, describes novela algorithms and circuitry for binary modulo-multiplication and combined multiplication-division. Unlike the commonly used Montgomery modular multiplier, no domain mapping is needed for the input operands or the output result. Further, the new algorithms work for both even and odd moduli. The combined multiplication-division algorithm produces the quotient as well as the remainder thus allowing the implementation of simple multiplier-dividers. The proposed algorithm uses left shift-based multiplication while maintaining the size of the intermediate running product contained by interleaving reduction and multiplication operations. Reduction is determined by examining only the two most significant bits of the running product if Carry-Propagate adders are used or the 3 most significant bits if Carry-Save Adders are used. Hardware implementations of the proposed algorithms show area and delay figures comparable to those of Montgomery.
| Original language | English |
|---|---|
| Pages (from-to) | 1797-1815 |
| Number of pages | 19 |
| Journal | Journal of Circuits, Systems and Computers |
| Volume | 19 |
| Issue number | 8 |
| DOIs | |
| State | Published - Dec 2010 |
Bibliographical note
Funding Information:The author would like to acknowledge King Abdul-Aziz City of Science & Technology for supporting this work under grant AR 22-17. The support of King Fahd University of Petroleum & Minerals is also greatly appreciated.
Keywords
- Computer arithmetic
- Montgomery multiplication
- cryptography
- high-speed arithmetic
- modular multiplication
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering