Abstract
PLAs with two-bit decoders at the inputs require a smaller area compared with standard two-level PLAs (Sasao 1984). The number of product rows required for such PLAs is a function of the assignment of pairs of variables to the decoders. This paper describes a minimization procedure that uses a genetic algorithm approach to reduce the size of two-bit decoder PLAs. Results are compared with those obtained by other approaches such as the Tomczuk and Miller heuristic (TMA) (1992) and the simulated annealing technique (Abd-El-Barr and Choy 1993). For large randomly generated test cases and bench-marks, our results are optimal or very near optimal.
| Original language | English |
|---|---|
| Pages (from-to) | 99-106 |
| Number of pages | 8 |
| Journal | International Journal of Electronics |
| Volume | 76 |
| Issue number | 1 |
| DOIs | |
| State | Published - Jan 1994 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
