TY - GEN
T1 - Functional test using behavior models
AU - Masud, Manzer
AU - Miczo, Alexander
AU - Betancourt, Rodolfo
AU - Karunaratne, Maddumage
PY - 1992/2
Y1 - 1992/2
N2 - The authors present a test synthesis system called TDX which uses functional information extracted from behavior models to generate high quality test vectors. TDX is designed to operate in a functional test mode or a fault-directed mode. In either of these two modes, fault simulation is performed on the resulting test sequences in order to compute the quality of the resulting test sequences. The main difference between these two modes of operation lies in the fact that functional test depends strictly on the behavioral model. TDX has been run on circuits ranging in size up to 80,000 gates. Some benchmarks were dominated by large state machines and/or counters that did not receive any DFT (design-for-testability) attention. In general, these benchmarks tended to be designs that companies have found to be difficult, if not impossible, for commercial gate-oriented ATPG (automatic test pattern generation) programs to handle. TDX has been quite successful on these benchmark circuits, achieving fault coverage of as much as 98% on circuits where conventional gate-level ATPGs did very poorly, and TDX has even outperformed engineers writing manual test programs.
AB - The authors present a test synthesis system called TDX which uses functional information extracted from behavior models to generate high quality test vectors. TDX is designed to operate in a functional test mode or a fault-directed mode. In either of these two modes, fault simulation is performed on the resulting test sequences in order to compute the quality of the resulting test sequences. The main difference between these two modes of operation lies in the fact that functional test depends strictly on the behavioral model. TDX has been run on circuits ranging in size up to 80,000 gates. Some benchmarks were dominated by large state machines and/or counters that did not receive any DFT (design-for-testability) attention. In general, these benchmarks tended to be designs that companies have found to be difficult, if not impossible, for commercial gate-oriented ATPG (automatic test pattern generation) programs to handle. TDX has been quite successful on these benchmark circuits, achieving fault coverage of as much as 98% on circuits where conventional gate-level ATPGs did very poorly, and TDX has even outperformed engineers writing manual test programs.
UR - https://www.scopus.com/pages/publications/0026819057
M3 - Conference contribution
AN - SCOPUS:0026819057
SN - 0818626550
T3 - Digest of Papers - IEEE Computer Society International Conference
SP - 446
EP - 451
BT - Digest of Papers - IEEE Computer Society International Conference
PB - Publ by IEEE
ER -