FPGA implementation of 64 bit Secure Force algorithm using full loop-unroll architecture

Shujaat Khan; M. Sohail Ibrahim; Haseeb Amjad; Kafeel Ahmed Khan; Mansoor Ebrahim

doi:10.1109/ICCSCE.2015.7482148

FPGA implementation of 64 bit Secure Force algorithm using full loop-unroll architecture

Shujaat Khan
, M. Sohail Ibrahim
, Haseeb Amjad
, Kafeel Ahmed Khan
, Mansoor Ebrahim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Field-Programmable Gate Arrays (FPGAs) have turned out to be a well-liked target for implementing cryptographic block ciphers. In this research work, recently proposed 64 bit Secure Force (SF) algorithm is implemented on an FPGA based full loop-unroll architecture. The proposed FPGA implementation of Secure Force yields a throughput of 2.3 Gbps for encryption, 2.6 Gbps for decryption, and 3.43 Gbps for key expansion at the cost of as low as 476, 400, and 160 slices for encryption, decryption, and key expansion respectively. The results obtained after extensive testing indicate that the throughput per unit area (throughput/slice) for the proposed implementation is comparable with many FPGA implementations of AES algorithm. The proposed design consumes 117.18 milli Watts thermal power.

Original language	English
Title of host publication	Proceedings - 5th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-6
Number of pages	6
ISBN (Electronic)	9781479982523
DOIs	https://doi.org/10.1109/ICCSCE.2015.7482148
State	Published - 31 May 2016
Externally published	Yes

Publication series

Name	Proceedings - 5th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2015

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

ASIC
FPGA
SF (Secure Force)
WSN (Wireless Sensor Networks);security algorithms
hardware implementation

ASJC Scopus subject areas

Computer Science Applications
Computer Vision and Pattern Recognition
Control and Systems Engineering
Artificial Intelligence

Access to Document

10.1109/ICCSCE.2015.7482148

Cite this

Khan, S., Ibrahim, M. S., Amjad, H., Khan, K. A., & Ebrahim, M. (2016). FPGA implementation of 64 bit Secure Force algorithm using full loop-unroll architecture. In Proceedings - 5th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2015 (pp. 1-6). Article 7482148 (Proceedings - 5th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCSCE.2015.7482148

Khan, Shujaat ; Ibrahim, M. Sohail ; Amjad, Haseeb et al. / FPGA implementation of 64 bit Secure Force algorithm using full loop-unroll architecture. Proceedings - 5th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2015. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 1-6 (Proceedings - 5th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2015).

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title = "FPGA implementation of 64 bit Secure Force algorithm using full loop-unroll architecture",

abstract = "Field-Programmable Gate Arrays (FPGAs) have turned out to be a well-liked target for implementing cryptographic block ciphers. In this research work, recently proposed 64 bit Secure Force (SF) algorithm is implemented on an FPGA based full loop-unroll architecture. The proposed FPGA implementation of Secure Force yields a throughput of 2.3 Gbps for encryption, 2.6 Gbps for decryption, and 3.43 Gbps for key expansion at the cost of as low as 476, 400, and 160 slices for encryption, decryption, and key expansion respectively. The results obtained after extensive testing indicate that the throughput per unit area (throughput/slice) for the proposed implementation is comparable with many FPGA implementations of AES algorithm. The proposed design consumes 117.18 milli Watts thermal power.",

keywords = "ASIC, FPGA, SF (Secure Force), WSN (Wireless Sensor Networks);security algorithms, hardware implementation",

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language = "English",

series = "Proceedings - 5th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2015",

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Khan, S , Ibrahim, MS, Amjad, H, Khan, KA & Ebrahim, M 2016, FPGA implementation of 64 bit Secure Force algorithm using full loop-unroll architecture. in Proceedings - 5th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2015., 7482148, Proceedings - 5th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2015, Institute of Electrical and Electronics Engineers Inc., pp. 1-6. https://doi.org/10.1109/ICCSCE.2015.7482148

FPGA implementation of 64 bit Secure Force algorithm using full loop-unroll architecture. / Khan, Shujaat ; Ibrahim, M. Sohail; Amjad, Haseeb et al.
Proceedings - 5th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2015. Institute of Electrical and Electronics Engineers Inc., 2016. p. 1-6 7482148 (Proceedings - 5th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Ibrahim, M. Sohail

AU - Amjad, Haseeb

AU - Khan, Kafeel Ahmed

AU - Ebrahim, Mansoor

PY - 2016/5/31

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N2 - Field-Programmable Gate Arrays (FPGAs) have turned out to be a well-liked target for implementing cryptographic block ciphers. In this research work, recently proposed 64 bit Secure Force (SF) algorithm is implemented on an FPGA based full loop-unroll architecture. The proposed FPGA implementation of Secure Force yields a throughput of 2.3 Gbps for encryption, 2.6 Gbps for decryption, and 3.43 Gbps for key expansion at the cost of as low as 476, 400, and 160 slices for encryption, decryption, and key expansion respectively. The results obtained after extensive testing indicate that the throughput per unit area (throughput/slice) for the proposed implementation is comparable with many FPGA implementations of AES algorithm. The proposed design consumes 117.18 milli Watts thermal power.

AB - Field-Programmable Gate Arrays (FPGAs) have turned out to be a well-liked target for implementing cryptographic block ciphers. In this research work, recently proposed 64 bit Secure Force (SF) algorithm is implemented on an FPGA based full loop-unroll architecture. The proposed FPGA implementation of Secure Force yields a throughput of 2.3 Gbps for encryption, 2.6 Gbps for decryption, and 3.43 Gbps for key expansion at the cost of as low as 476, 400, and 160 slices for encryption, decryption, and key expansion respectively. The results obtained after extensive testing indicate that the throughput per unit area (throughput/slice) for the proposed implementation is comparable with many FPGA implementations of AES algorithm. The proposed design consumes 117.18 milli Watts thermal power.

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Khan S , Ibrahim MS, Amjad H, Khan KA, Ebrahim M. FPGA implementation of 64 bit Secure Force algorithm using full loop-unroll architecture. In Proceedings - 5th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2015. Institute of Electrical and Electronics Engineers Inc. 2016. p. 1-6. 7482148. (Proceedings - 5th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2015). doi: 10.1109/ICCSCE.2015.7482148

FPGA implementation of 64 bit Secure Force algorithm using full loop-unroll architecture

Abstract

Publication series

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this