Abstract
In this paper a formal design methodology is used to design a Residue Number System (RNS) processor. An optimal architecture for the residue decoding process is obtained through this design approach. The architecture is modular, consists of simple cells, and is general for any set of moduli.
| Original language | English |
|---|---|
| Pages | 605-608 |
| Number of pages | 4 |
| State | Published - 1991 |
ASJC Scopus subject areas
- General Engineering