Finite state machine-based fault tolerance technique with enhanced area and power of synthesised sequential circuits

Aiman H. El-Maleh*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

Recently, a finite state machine-based fault tolerance technique for sequential circuits based on protecting few states with high probability of occurrence has been proposed. In this study, the authors propose an algorithm that starts with a given state assignment targeting the optimisation of either area or power and generates a state assignment that preserves the original state assignment and satisfies the fault tolerance requirements for the protected states. Experimental results demonstrate the effectiveness of the proposed algorithm in significantly reducing the area and power of synthesised sequential circuits while enhancing their fault tolerance.

Original languageEnglish
Pages (from-to)159-164
Number of pages6
JournalIET Computers and Digital Techniques
Volume11
Issue number4
DOIs
StatePublished - 1 Jul 2017

Bibliographical note

Publisher Copyright:
© The Institution of Engineering and Technology 2017.

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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