FBNoC: FPGA-based network on chip emulator for full-system architectural simulation of many-core systems

SoCs and chip multi processors (CMPs) usually employ a scalable interconnection network (Network-on-chip or NoC) as a communication medium. Existing simulators that can simulate such systems are mostly SW based and as such are very slow. Fast FPGA-based hardware simulators of CMP systems are gaining popularity because they allow fast and efficient exploration of several design points with multiple benchmarks. This entail emulating the NoC in these systems with different parameters and configurations. Existing hardware NoC simulators that are implemented on Field Programmable Gate Arrays (FPGAs) are not readily integrate-able with other FPGA-based multicore architectural simulators. In this work, a new FPGA-based NoC emulator (FBNoC) that can be integrated with multicore architectural simulators is proposed. It can also be used as a standalone NoC simulator. Utilizing a parametrizable latency model, FBNoC can deliver packets and accurately estimate their latencies for several NoC topologies, configurations, and parameters without the need for re-synthesize nor FPGA re-configuration. It also employs a novel multi-local port per NoC node strategy combined with two bidirectional ring networks to reduce the FPGA resource utilization while increasing the simulation speed. Requiring less FPGA resources than other FPGA-based NoC simulators, the proposed emulator can achieve more than 20,000x speedup over the popular SW NoC simulator Booksim.