Fast and Flexible Architectures for RNS Arithmetic Decoding

Khaled M. Elleithy; Magdy A. Bayoumi

doi:10.1109/82.136572

Fast and Flexible Architectures for RNS Arithmetic Decoding

Khaled M. Elleithy, Magdy A. Bayoumi

King Fahd University of Petroleum & Minerals

Research output: Contribution to journal › Article › peer-review

55 Scopus citations

Abstract

An implementation of a fast and flexible residue decoder for residue number system (RNS)-based architectures is proposed. The decoder is based on the Chinese Remainder Theorem (CRT). It decodes a set of residues to its equivalent representation in weighted binary number system. This decoder is flexible since the decoded data can be selected to be either unsigned magnitude or 2's complement binary number. Two different architectures are analyzed; the first one is based on using carry-save adders (CSA's), while the other is based on utilizing modulo adders (MA). The implementation of both architectures is modular and is based on simple cells, which leads to efficient VLSI realization. The proposed decoder is fast; it has a time complexity of θ(log N) (N is the number of moduli).

Original language	English
Pages (from-to)	226-235
Number of pages	10
Journal	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume	39
Issue number	4
DOIs	https://doi.org/10.1109/82.136572
State	Published - May 1992

Keywords

Chinese remainder theorem
Residue number system
carry-save adder
finite field algorithm
modulo adder
residue decoding

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering

Access to Document

10.1109/82.136572

Cite this

@article{4d79f868f84b4458a5f0eb95af738dcc,

title = "Fast and Flexible Architectures for RNS Arithmetic Decoding",

abstract = "An implementation of a fast and flexible residue decoder for residue number system (RNS)-based architectures is proposed. The decoder is based on the Chinese Remainder Theorem (CRT). It decodes a set of residues to its equivalent representation in weighted binary number system. This decoder is flexible since the decoded data can be selected to be either unsigned magnitude or 2's complement binary number. Two different architectures are analyzed; the first one is based on using carry-save adders (CSA's), while the other is based on utilizing modulo adders (MA). The implementation of both architectures is modular and is based on simple cells, which leads to efficient VLSI realization. The proposed decoder is fast; it has a time complexity of θ(log N) (N is the number of moduli).",

keywords = "Chinese remainder theorem, Residue number system, carry-save adder, finite field algorithm, modulo adder, residue decoding",

author = "Elleithy, \{Khaled M.\} and Bayoumi, \{Magdy A.\}",

year = "1992",

month = may,

doi = "10.1109/82.136572",

language = "English",

volume = "39",

pages = "226--235",

journal = "IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing",

issn = "1057-7130",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - Fast and Flexible Architectures for RNS Arithmetic Decoding

AU - Elleithy, Khaled M.

AU - Bayoumi, Magdy A.

PY - 1992/5

Y1 - 1992/5

N2 - An implementation of a fast and flexible residue decoder for residue number system (RNS)-based architectures is proposed. The decoder is based on the Chinese Remainder Theorem (CRT). It decodes a set of residues to its equivalent representation in weighted binary number system. This decoder is flexible since the decoded data can be selected to be either unsigned magnitude or 2's complement binary number. Two different architectures are analyzed; the first one is based on using carry-save adders (CSA's), while the other is based on utilizing modulo adders (MA). The implementation of both architectures is modular and is based on simple cells, which leads to efficient VLSI realization. The proposed decoder is fast; it has a time complexity of θ(log N) (N is the number of moduli).

AB - An implementation of a fast and flexible residue decoder for residue number system (RNS)-based architectures is proposed. The decoder is based on the Chinese Remainder Theorem (CRT). It decodes a set of residues to its equivalent representation in weighted binary number system. This decoder is flexible since the decoded data can be selected to be either unsigned magnitude or 2's complement binary number. Two different architectures are analyzed; the first one is based on using carry-save adders (CSA's), while the other is based on utilizing modulo adders (MA). The implementation of both architectures is modular and is based on simple cells, which leads to efficient VLSI realization. The proposed decoder is fast; it has a time complexity of θ(log N) (N is the number of moduli).

KW - Chinese remainder theorem

KW - Residue number system

KW - carry-save adder

KW - finite field algorithm

KW - modulo adder

KW - residue decoding

UR - https://www.scopus.com/pages/publications/0026852363

U2 - 10.1109/82.136572

DO - 10.1109/82.136572

M3 - Article

AN - SCOPUS:0026852363

SN - 1057-7130

VL - 39

SP - 226

EP - 235

JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

IS - 4

ER -

Fast and Flexible Architectures for RNS Arithmetic Decoding

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Fingerprint

Cite this