Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor with Synthesizable PLL

Austin Rovinski; Bandhav Veluri; Anuj Rao; Tutu Ajayi; Julian Puscar; Steve Dai; Ritchie Zhao; Dustin Richmond; Zhiru Zhang; Ian Galton; Christopher Batten; Chun Zhao; Michael B. Taylor; Ronald G. Dreslinski; Khalid Al-Hawaj; Paul Gao; Shaolin Xie; Christopher Torng; Scott Davidson; Aporva Amarnath; Luis Vega

doi:10.1109/LSSC.2019.2953847

Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor with Synthesizable PLL

Austin Rovinski^*
, Bandhav Veluri
, Anuj Rao
, Tutu Ajayi
, Julian Puscar
, Steve Dai
, Ritchie Zhao
, Dustin Richmond
, Zhiru Zhang
, Ian Galton
, Christopher Batten
, Chun Zhao
, Michael B. Taylor
, Ronald G. Dreslinski
, Khalid Al-Hawaj
, Paul Gao
, Shaolin Xie
, Christopher Torng
, Scott Davidson
, Aporva Amarnath

Luis Vega

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

20 Scopus citations

Abstract

This letter presents a 16-nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4 GHz at 0.98 V, yielding a peak throughput of 695 Giga RISC-V instructions/s (GRVIS), a peak energy efficiency of 314.89 GRVIS/W, and a record 825 320 CoreMark benchmark score. Unlike previously reported [1], this new score was obtained without modifying the core benchmark code. The main feature is the NoC architecture, which uses only 1881~\mu \text{m}^{2} per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.

Original language	English
Article number	8903494
Pages (from-to)	289-292
Number of pages	4
Journal	IEEE Solid-State Circuits Letters
Volume	2
Issue number	12
DOIs	https://doi.org/10.1109/LSSC.2019.2953847
State	Published - Dec 2019
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

Celerity
RISC-V
manycore
network-on-chip (NoC)

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/LSSC.2019.2953847

Cite this

Rovinski, A., Veluri, B., Rao, A., Ajayi, T., Puscar, J., Dai, S., Zhao, R., Richmond, D., Zhang, Z., Galton, I., Batten, C., Zhao, C., Taylor, M. B., Dreslinski, R. G., Al-Hawaj, K., Gao, P., Xie, S., Torng, C., Davidson, S., ... Vega, L. (2019). Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor with Synthesizable PLL. IEEE Solid-State Circuits Letters, 2(12), 289-292. Article 8903494. https://doi.org/10.1109/LSSC.2019.2953847

@article{f658fa5ff9d34abeaba16d5214961b23,

title = "Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor with Synthesizable PLL",

abstract = "This letter presents a 16-nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4 GHz at 0.98 V, yielding a peak throughput of 695 Giga RISC-V instructions/s (GRVIS), a peak energy efficiency of 314.89 GRVIS/W, and a record 825 320 CoreMark benchmark score. Unlike previously reported [1], this new score was obtained without modifying the core benchmark code. The main feature is the NoC architecture, which uses only 1881\textasciitilde{}\textbackslash{}mu \textbackslash{}text\{m\}\textasciicircum{}\{2\} per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.",

keywords = "Celerity, RISC-V, manycore, network-on-chip (NoC)",

author = "Austin Rovinski and Bandhav Veluri and Anuj Rao and Tutu Ajayi and Julian Puscar and Steve Dai and Ritchie Zhao and Dustin Richmond and Zhiru Zhang and Ian Galton and Christopher Batten and Chun Zhao and Taylor, \{Michael B.\} and Dreslinski, \{Ronald G.\} and Khalid Al-Hawaj and Paul Gao and Shaolin Xie and Christopher Torng and Scott Davidson and Aporva Amarnath and Luis Vega",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.",

year = "2019",

month = dec,

doi = "10.1109/LSSC.2019.2953847",

language = "English",

volume = "2",

pages = "289--292",

journal = "IEEE Solid-State Circuits Letters",

issn = "2573-9603",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "12",

}

Rovinski, A, Veluri, B, Rao, A, Ajayi, T, Puscar, J, Dai, S, Zhao, R, Richmond, D, Zhang, Z, Galton, I, Batten, C, Zhao, C, Taylor, MB, Dreslinski, RG, Al-Hawaj, K, Gao, P, Xie, S, Torng, C, Davidson, S, Amarnath, A & Vega, L 2019, 'Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor with Synthesizable PLL', IEEE Solid-State Circuits Letters, vol. 2, no. 12, 8903494, pp. 289-292. https://doi.org/10.1109/LSSC.2019.2953847

TY - JOUR

T1 - Evaluating Celerity

T2 - A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor with Synthesizable PLL

AU - Rovinski, Austin

AU - Veluri, Bandhav

AU - Rao, Anuj

AU - Ajayi, Tutu

AU - Puscar, Julian

AU - Dai, Steve

AU - Zhao, Ritchie

AU - Richmond, Dustin

AU - Zhang, Zhiru

AU - Galton, Ian

AU - Batten, Christopher

AU - Zhao, Chun

AU - Taylor, Michael B.

AU - Dreslinski, Ronald G.

AU - Al-Hawaj, Khalid

AU - Gao, Paul

AU - Xie, Shaolin

AU - Torng, Christopher

AU - Davidson, Scott

AU - Amarnath, Aporva

AU - Vega, Luis

PY - 2019/12

Y1 - 2019/12

N2 - This letter presents a 16-nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4 GHz at 0.98 V, yielding a peak throughput of 695 Giga RISC-V instructions/s (GRVIS), a peak energy efficiency of 314.89 GRVIS/W, and a record 825 320 CoreMark benchmark score. Unlike previously reported [1], this new score was obtained without modifying the core benchmark code. The main feature is the NoC architecture, which uses only 1881~\mu \text{m}^{2} per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.

AB - This letter presents a 16-nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4 GHz at 0.98 V, yielding a peak throughput of 695 Giga RISC-V instructions/s (GRVIS), a peak energy efficiency of 314.89 GRVIS/W, and a record 825 320 CoreMark benchmark score. Unlike previously reported [1], this new score was obtained without modifying the core benchmark code. The main feature is the NoC architecture, which uses only 1881~\mu \text{m}^{2} per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.

KW - Celerity

KW - RISC-V

KW - manycore

KW - network-on-chip (NoC)

UR - https://www.scopus.com/pages/publications/85082546625

U2 - 10.1109/LSSC.2019.2953847

DO - 10.1109/LSSC.2019.2953847

M3 - Article

AN - SCOPUS:85082546625

SN - 2573-9603

VL - 2

SP - 289

EP - 292

JO - IEEE Solid-State Circuits Letters

JF - IEEE Solid-State Circuits Letters

IS - 12

M1 - 8903494

ER -

Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor with Synthesizable PLL

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Fingerprint

Cite this