Error control coding for multi-level cell memories

The ever increasing demand to store huge amounts of data at affordable prices has led to the widespread usage of multi level cell (MLC) memory devices. These memories have the capability to store multiple numbers of bits per cell, thus increasing the capacity with minimal effect on hardware. This increase, however, comes at the price of reliability; more bits per cell results in more chances of error and thus less reliability. Error control coding is widely employed to improve the reliability of data that has been read. This paper proposes a new scheme for error correction in multilevel cell memories. The process involves splitting the contents of the memory cells into i symbols and assigning them to i different codewords. Encoding and decoding are performed using the same code but over i iterations. The scheme exhibits an apparent error correction advantage over polyvalent-based schemes.