Efficient Leading Zero Count (LZC) Implementations for Xilinx FPGAs

Leading zero count (LZC) is a fundamental building block in floating-point arithmetic and data sketches. These applications are increasingly being implemented on field-programmable gate arrays (FPGAs), however, existing architectures for LZC target application-specific integrated circuits and to the best of our knowledge specific LZC implementations tailored to FPGA structures have not been presented. In this letter, the implementation of LZC on Xilinx FPGA is considered and it is shown that by carefully adapting the LZC design to the FPGA structure, more efficient implementations can be obtained. In more detail, LZC designs for different bit widths are presented and evaluated. The results show that significant reductions in the FPGA resources needed are obtained that reach 33% lookup tables (LUTs) saving for 32-bit vectors and 20% LUTs saving for 64-bit vectors.