Efficient CMOL nanoscale hybrid circuit cell assignment using simulated evolution heuristic

Recently, many CMOS/nanodevices hybrid architectures have been proposed, the new architectures combine the flexibility and high fabrication yield advantages of CMOS technology with nanometer scale latching devices. CMOL, a novel architecture that uses two levels of perpendicular nanowires as crossbar interconnection on top of inverter-based CMOS stack, offers significant density advantages and overcomes physical barriers of lithography-based fabrication. However, the confined connectivity of CMOL nanofabric to only cells that are located within proximity square-like connectivity domain, reduces the flexibility of VLSI design automation and further complicates cells placement. In this paper we use Simulated Evolution algorithm to solve the NP-hard problem of assigning NOR/INV gates to CMOL array. The main objective is to reduce the total number of buffers that must be inserted between cells that require long wires to connect. A novel goodness and allocation functions are introduced for efficient exploration of search space. Empirical results for ISCAS'89 benchmarks are compared with previous solutions using GA, MA, and LRMA heuristics. Our approach is able to find better solutions for all tested benchmarks and with 82% average reduction in CPU processing time.