Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs

Ernesto Sanchez; Luca Sterpone; Anees Ullah

doi:10.1109/FPL.2014.6927478

Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs

Ernesto Sanchez
, Luca Sterpone
, Anees Ullah

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

Hardware fault emulation for Application Specific Integrated Circuits (ASICs) on FPGAs can considerably reduce the time required for the fault simulation. This paper presents a methodology to emulate ASIC faults on state-of-the-art FPGAs. The fault emulation is achieved by following a fully automated process consisting of: constrained technology mapping of ASIC net-list; creation of fault dictionary, generation of faulty partial bit-streams and fault emulation. The proposed approach exploits run-time partial reconfiguration techniques for fault injection and avoids full net-list re-compilations. The method's feasibility is assessed through carefully selected circuits and overhead in terms of area and timing is reported.

Original language	English
Title of host publication	Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9783000446450
DOIs	https://doi.org/10.1109/FPL.2014.6927478
State	Published - 16 Oct 2014

Publication series

Name	Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014

Bibliographical note

Publisher Copyright:
© 2014 Technical University of Munich (TUM).

Keywords

Hardware Fault Emulation (HFE)
Run-Time Reconfiguration (RTR)
Software Fault Simulation (SFS)

ASJC Scopus subject areas

Computer Science Applications
Hardware and Architecture

Access to Document

10.1109/FPL.2014.6927478

Cite this

Sanchez, E., Sterpone, L., & Ullah, A. (2014). Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs. In Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014 Article 6927478 (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPL.2014.6927478

Sanchez, Ernesto ; Sterpone, Luca ; Ullah, Anees. / Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs. Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 2014. (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014).

@inproceedings{962659ae6f014ceea5a524669a024a40,

title = "Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs",

abstract = "Hardware fault emulation for Application Specific Integrated Circuits (ASICs) on FPGAs can considerably reduce the time required for the fault simulation. This paper presents a methodology to emulate ASIC faults on state-of-the-art FPGAs. The fault emulation is achieved by following a fully automated process consisting of: constrained technology mapping of ASIC net-list; creation of fault dictionary, generation of faulty partial bit-streams and fault emulation. The proposed approach exploits run-time partial reconfiguration techniques for fault injection and avoids full net-list re-compilations. The method's feasibility is assessed through carefully selected circuits and overhead in terms of area and timing is reported.",

keywords = "Hardware Fault Emulation (HFE), Run-Time Reconfiguration (RTR), Software Fault Simulation (SFS)",

author = "Ernesto Sanchez and Luca Sterpone and Anees Ullah",

note = "Publisher Copyright: {\textcopyright} 2014 Technical University of Munich (TUM).",

year = "2014",

month = oct,

day = "16",

doi = "10.1109/FPL.2014.6927478",

language = "English",

series = "Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014",

address = "United States",

}

Sanchez, E, Sterpone, L & Ullah, A 2014, Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs. in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014., 6927478, Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1109/FPL.2014.6927478

Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs. / Sanchez, Ernesto; Sterpone, Luca; Ullah, Anees.
Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6927478 (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs

AU - Sanchez, Ernesto

AU - Sterpone, Luca

AU - Ullah, Anees

PY - 2014/10/16

Y1 - 2014/10/16

N2 - Hardware fault emulation for Application Specific Integrated Circuits (ASICs) on FPGAs can considerably reduce the time required for the fault simulation. This paper presents a methodology to emulate ASIC faults on state-of-the-art FPGAs. The fault emulation is achieved by following a fully automated process consisting of: constrained technology mapping of ASIC net-list; creation of fault dictionary, generation of faulty partial bit-streams and fault emulation. The proposed approach exploits run-time partial reconfiguration techniques for fault injection and avoids full net-list re-compilations. The method's feasibility is assessed through carefully selected circuits and overhead in terms of area and timing is reported.

AB - Hardware fault emulation for Application Specific Integrated Circuits (ASICs) on FPGAs can considerably reduce the time required for the fault simulation. This paper presents a methodology to emulate ASIC faults on state-of-the-art FPGAs. The fault emulation is achieved by following a fully automated process consisting of: constrained technology mapping of ASIC net-list; creation of fault dictionary, generation of faulty partial bit-streams and fault emulation. The proposed approach exploits run-time partial reconfiguration techniques for fault injection and avoids full net-list re-compilations. The method's feasibility is assessed through carefully selected circuits and overhead in terms of area and timing is reported.

KW - Hardware Fault Emulation (HFE)

KW - Run-Time Reconfiguration (RTR)

KW - Software Fault Simulation (SFS)

UR - https://www.scopus.com/pages/publications/84911091886

U2 - 10.1109/FPL.2014.6927478

DO - 10.1109/FPL.2014.6927478

M3 - Conference contribution

AN - SCOPUS:84911091886

T3 - Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014

BT - Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Sanchez E, Sterpone L, Ullah A. Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs. In Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6927478. (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014). doi: 10.1109/FPL.2014.6927478

Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs

Abstract

Publication series

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Fingerprint

Cite this