Double-rail encoded self-timed adder with matched delays

Alaaeldin Amin; Feras Maadi

doi:10.1109/ICECS.2003.1301721

Double-rail encoded self-timed adder with matched delays

Alaaeldin Amin^*, Feras Maadi

^*Corresponding author for this work

King Fahd University of Petroleum & Minerals

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

An efficient self-timed adder with low area overhead and efficient acknowledge slack time is proposed. The adder uses double-rail encoding of the carry signals as well as process-tracking matching delays to guarantee proper generation of the completion signal.

Original language	English
Title of host publication	ICECS 2003 - Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems
Pages	1172-1175
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.2003.1301721
State	Published - 2003

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	3

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ICECS.2003.1301721

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Amin, A., & Maadi, F. (2003). Double-rail encoded self-timed adder with matched delays. In ICECS 2003 - Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems (pp. 1172-1175). Article 1301721 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 3). https://doi.org/10.1109/ICECS.2003.1301721

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title = "Double-rail encoded self-timed adder with matched delays",

abstract = "An efficient self-timed adder with low area overhead and efficient acknowledge slack time is proposed. The adder uses double-rail encoding of the carry signals as well as process-tracking matching delays to guarantee proper generation of the completion signal.",

author = "Alaaeldin Amin and Feras Maadi",

year = "2003",

doi = "10.1109/ICECS.2003.1301721",

language = "English",

isbn = "0780381637",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

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Double-rail encoded self-timed adder with matched delays. / Amin, Alaaeldin; Maadi, Feras.
ICECS 2003 - Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems. 2003. p. 1172-1175 1301721 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Double-rail encoded self-timed adder with matched delays

AU - Amin, Alaaeldin

AU - Maadi, Feras

PY - 2003

Y1 - 2003

N2 - An efficient self-timed adder with low area overhead and efficient acknowledge slack time is proposed. The adder uses double-rail encoding of the carry signals as well as process-tracking matching delays to guarantee proper generation of the completion signal.

AB - An efficient self-timed adder with low area overhead and efficient acknowledge slack time is proposed. The adder uses double-rail encoding of the carry signals as well as process-tracking matching delays to guarantee proper generation of the completion signal.

UR - https://www.scopus.com/pages/publications/77956045413

U2 - 10.1109/ICECS.2003.1301721

DO - 10.1109/ICECS.2003.1301721

M3 - Conference contribution

AN - SCOPUS:77956045413

SN - 0780381637

SN - 9780780381636

T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

SP - 1172

EP - 1175

BT - ICECS 2003 - Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems

ER -

Double-rail encoded self-timed adder with matched delays

Abstract

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ASJC Scopus subject areas

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