TY - GEN
T1 - Discrete-time full and reduced order anti-windup compensator synthesis for constraint cascade control systems
T2 - 2009 International Conference on Emerging Technologies, ICET 2009
AU - Rehan, Muhammad
AU - Ahmed, Abrar
AU - Iqbal, Naeem
PY - 2009/12/9
Y1 - 2009/12/9
N2 - In this paper, discrete-time full and reduced order anti-windup design for general linear cascade control systems under actuator saturation constraint is considered. Based on decoupled architecture with multi-loop compensation, l 2 gain reduction, discrete-time Block Diagonal Quadratic Lyapunov Function, and sector bounded-ness, LMI conditions are developed for full and reduced order anti-windup design which guarantees the stability and performance of overall closed-loop system. Results are demonstrated through a simulation example from process control.
AB - In this paper, discrete-time full and reduced order anti-windup design for general linear cascade control systems under actuator saturation constraint is considered. Based on decoupled architecture with multi-loop compensation, l 2 gain reduction, discrete-time Block Diagonal Quadratic Lyapunov Function, and sector bounded-ness, LMI conditions are developed for full and reduced order anti-windup design which guarantees the stability and performance of overall closed-loop system. Results are demonstrated through a simulation example from process control.
KW - Discretetime cascade control systems
KW - Full and reduced order antiwindup compensator
KW - L gain
KW - Linear matrix inequalities (LMIs)
KW - Multi-loop compensation
UR - https://www.scopus.com/pages/publications/76549093547
U2 - 10.1109/ICET.2009.5353148
DO - 10.1109/ICET.2009.5353148
M3 - Conference contribution
AN - SCOPUS:76549093547
SN - 9781424456338
T3 - 2009 International Conference on Emerging Technologies, ICET 2009
SP - 347
EP - 351
BT - 2009 International Conference on Emerging Technologies, ICET 2009
Y2 - 19 October 2009 through 20 October 2009
ER -