DFT technique for rf plls using built-in monitors

On-chip test measures for new generation analog and mixedsignal RF circuits will replace performances that are becoming too costly or impossible to measure on-chip and/or on-tester. On one hand, these on-chip measurements must not degrade the DUT performances during the operation mode. On the other hand they must be highly correlated with the circuit performances. They should help to reduce test time and resources for production test while maintaining standard quality. For RF PLLs, the measurement of performances such as jitter, for example, is becoming unfeasible with increasing frequencies. This paper presents a Dff technique for RF PLLs using three built-in monitors that take measures highly correlated with device performances. A simple lock state test is required in a low cost digital tester. The built-in monitors are intended to give a Go/No-Go digital output. An evaluation of catastrophic fault coverage of the test technique is carried out on the VCO block through fault simulation. Parametric yield loss and defect level are evaluated using a statistical model of the VCO obtained by a Copulas-based probability density estimation technique. The case-study is a 65 nm CMOS RF PLL designed and manufactured at STMicroelectronics.