Designing a Second Order Generalized Integrator Digital Phase Locked Loop based on a Frequency Response Approach

Tiago Davi Curi Busarello; Kamran Zeb; Adriano Peres; V. S.R.Varaprasad Oruganti; Marcelo Godoy Simões

doi:10.1109/ISGT-LA.2019.8895304

Designing a Second Order Generalized Integrator Digital Phase Locked Loop based on a Frequency Response Approach

Tiago Davi Curi Busarello, Kamran Zeb, Adriano Peres, V. S.R.Varaprasad Oruganti, Marcelo Godoy Simões

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

This paper presents a Digital Phase-Locked Loop (PLL) based on the Second Order Generalized Integrator (SOGI). The PLL structure, as well as the SOGI, are carefully described. The integrators of the SOGI are explained in detail in order to emphasize the elimination of an algebraic loop found in continuous time domain PLLs. The main contributions of this paper are to present the design of PLL entirely in z-domain and to present an easy, fast and accurate way to implement a digital PLL based on the SOGI structure. The digital SOGI PLL is implemented in the digital signal processor TMS320F28335. Experimental and simulation results show the efficacy of the digital SOGI PLL to keep synchronized with grid voltage at frequencies 50 and 60 Hz.

Original language	English
Title of host publication	2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538695678
DOIs	https://doi.org/10.1109/ISGT-LA.2019.8895304
State	Published - Sep 2019
Externally published	Yes
Event	2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019 - Gramado, Brazil Duration: 15 Sep 2019 → 18 Sep 2019

Publication series

Name	2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019

Conference

Conference	2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019
Country/Territory	Brazil
City	Gramado
Period	15/09/19 → 18/09/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

Keywords

backward integrator
forward integrator
Phase locked loops
SOGI

ASJC Scopus subject areas

Electrical and Electronic Engineering
Control and Optimization
Artificial Intelligence
Energy Engineering and Power Technology
Renewable Energy, Sustainability and the Environment

Access to Document

10.1109/ISGT-LA.2019.8895304

Cite this

Busarello, T. D. C., Zeb, K., Peres, A., Oruganti, V. S. R. V., & Simões, M. G. (2019). Designing a Second Order Generalized Integrator Digital Phase Locked Loop based on a Frequency Response Approach. In 2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019 Article 8895304 (2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISGT-LA.2019.8895304

Busarello, Tiago Davi Curi ; Zeb, Kamran ; Peres, Adriano et al. / Designing a Second Order Generalized Integrator Digital Phase Locked Loop based on a Frequency Response Approach. 2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019).

@inproceedings{db61c0c0dcf7486bb5fb73201105bdfb,

title = "Designing a Second Order Generalized Integrator Digital Phase Locked Loop based on a Frequency Response Approach",

abstract = "This paper presents a Digital Phase-Locked Loop (PLL) based on the Second Order Generalized Integrator (SOGI). The PLL structure, as well as the SOGI, are carefully described. The integrators of the SOGI are explained in detail in order to emphasize the elimination of an algebraic loop found in continuous time domain PLLs. The main contributions of this paper are to present the design of PLL entirely in z-domain and to present an easy, fast and accurate way to implement a digital PLL based on the SOGI structure. The digital SOGI PLL is implemented in the digital signal processor TMS320F28335. Experimental and simulation results show the efficacy of the digital SOGI PLL to keep synchronized with grid voltage at frequencies 50 and 60 Hz.",

keywords = "backward integrator, forward integrator, Phase locked loops, SOGI",

author = "Busarello, {Tiago Davi Curi} and Kamran Zeb and Adriano Peres and Oruganti, {V. S.R.Varaprasad} and Sim{\~o}es, {Marcelo Godoy}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019 ; Conference date: 15-09-2019 Through 18-09-2019",

year = "2019",

month = sep,

doi = "10.1109/ISGT-LA.2019.8895304",

language = "English",

series = "2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019",

address = "United States",

}

Busarello, TDC, Zeb, K, Peres, A, Oruganti, VSRV & Simões, MG 2019, Designing a Second Order Generalized Integrator Digital Phase Locked Loop based on a Frequency Response Approach. in 2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019., 8895304, 2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019, Gramado, Brazil, 15/09/19. https://doi.org/10.1109/ISGT-LA.2019.8895304

Designing a Second Order Generalized Integrator Digital Phase Locked Loop based on a Frequency Response Approach. / Busarello, Tiago Davi Curi; Zeb, Kamran; Peres, Adriano et al.
2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8895304 (2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Designing a Second Order Generalized Integrator Digital Phase Locked Loop based on a Frequency Response Approach

AU - Busarello, Tiago Davi Curi

AU - Zeb, Kamran

AU - Peres, Adriano

AU - Oruganti, V. S.R.Varaprasad

AU - Simões, Marcelo Godoy

PY - 2019/9

Y1 - 2019/9

N2 - This paper presents a Digital Phase-Locked Loop (PLL) based on the Second Order Generalized Integrator (SOGI). The PLL structure, as well as the SOGI, are carefully described. The integrators of the SOGI are explained in detail in order to emphasize the elimination of an algebraic loop found in continuous time domain PLLs. The main contributions of this paper are to present the design of PLL entirely in z-domain and to present an easy, fast and accurate way to implement a digital PLL based on the SOGI structure. The digital SOGI PLL is implemented in the digital signal processor TMS320F28335. Experimental and simulation results show the efficacy of the digital SOGI PLL to keep synchronized with grid voltage at frequencies 50 and 60 Hz.

AB - This paper presents a Digital Phase-Locked Loop (PLL) based on the Second Order Generalized Integrator (SOGI). The PLL structure, as well as the SOGI, are carefully described. The integrators of the SOGI are explained in detail in order to emphasize the elimination of an algebraic loop found in continuous time domain PLLs. The main contributions of this paper are to present the design of PLL entirely in z-domain and to present an easy, fast and accurate way to implement a digital PLL based on the SOGI structure. The digital SOGI PLL is implemented in the digital signal processor TMS320F28335. Experimental and simulation results show the efficacy of the digital SOGI PLL to keep synchronized with grid voltage at frequencies 50 and 60 Hz.

KW - backward integrator

KW - forward integrator

KW - Phase locked loops

KW - SOGI

UR - http://www.scopus.com/inward/record.url?scp=85075715298&partnerID=8YFLogxK

U2 - 10.1109/ISGT-LA.2019.8895304

DO - 10.1109/ISGT-LA.2019.8895304

M3 - Conference contribution

AN - SCOPUS:85075715298

T3 - 2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019

BT - 2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019

Y2 - 15 September 2019 through 18 September 2019

ER -

Busarello TDC, Zeb K, Peres A, Oruganti VSRV, Simões MG. Designing a Second Order Generalized Integrator Digital Phase Locked Loop based on a Frequency Response Approach. In 2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8895304. (2019 IEEE PES Conference on Innovative Smart Grid Technologies, ISGT Latin America 2019). doi: 10.1109/ISGT-LA.2019.8895304

Designing a Second Order Generalized Integrator Digital Phase Locked Loop based on a Frequency Response Approach

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this