Design, synthesis and implementation of 8-bit accumulator using FPGA Board

Accumulators are frequently used in digital circuits to store and process bi-nary data. The functionality of the accumulator is identical to a counter. In-stead of incrementing the counter value by a constant, the accumulator adds the input value to the current value. Using Verilog programming, an 8-bit accumulator was designed. In this work, to implement an 8-bit accumulator including functions: multiplication, division, and modulus. From the con-ducted simulation, the operations of 8-bit accumulator performs different operations based on different modes of operations along with displaying the results on FPGA. The Verilog HDL is used to design and simulate accumulator on Xilinx Vivado and generated bitstream files are uploaded to Nexys-4 Artix-7 FPGA board to show the result through the built-in seven-segment display. A Verilog top module is used to map the inputs parameters to the available onboard switches and push buttons to perform different operations and saving the results on accumulator. The internal clock of the board is 450 MHz and reduced to 10 Hz for an 8-bit accumulator and 10kHz for a seven-segment display using a clock divider.