Design, selection and implementation of flash erase EEPROM memory cells

The paper reports an investigation into the design and process constraints of FLASH EEPROM memory cells. It describes several possible structures which were developed by the MOS memory R&D group of National Semiconductor Corporation at West Jordan, Utah. These structures were implemented and tested on a specially designed test chip. In addition to the typical structures of poly 1 floating gate and poly 2 control gate, new novel structures of poly 2 floating gate and poly 1 control gate were implemented. A total of 5 major structures are described. The paper discusses the principle of operation, advantages and disadvantages of each of these structures. It also includes characteristic results and discussion of the performance of these candidate cells.