Design of a programmable length FIFO memory andits controller

Munir A. Kulaib; Gerhard F. Beckhoff; Sadiq M. Sait

doi:10.1080/00207218808945291

Design of a programmable length FIFO memory andits controller

Munir A. Kulaib, Gerhard F. Beckhoff, Sadiq M. Sait

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

This paper describes the CMOS design of a first-in, first-out (FIFO) memory. The design is based on 2μ. meter CMOStechnology and can operate with a 20 MHz clock. The length of the FIFO is programmable, resulting in minimum data ripple throughtime, for applications not requiring the full length.

Original language	English
Pages (from-to)	923-932
Number of pages	10
Journal	International Journal of Electronics
Volume	65
Issue number	5
DOIs	https://doi.org/10.1080/00207218808945291
State	Published - Nov 1988

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1080/00207218808945291

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title = "Design of a programmable length FIFO memory andits controller",

abstract = "This paper describes the CMOS design of a first-in, first-out (FIFO) memory. The design is based on 2μ. meter CMOStechnology and can operate with a 20 MHz clock. The length of the FIFO is programmable, resulting in minimum data ripple throughtime, for applications not requiring the full length.",

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AB - This paper describes the CMOS design of a first-in, first-out (FIFO) memory. The design is based on 2μ. meter CMOStechnology and can operate with a 20 MHz clock. The length of the FIFO is programmable, resulting in minimum data ripple throughtime, for applications not requiring the full length.

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Design of a programmable length FIFO memory andits controller

Abstract

ASJC Scopus subject areas

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