@inproceedings{0899ec3db3914185bf85bb46fe769eff,
title = "Design of a high throughput 128-bit AES (Rijndael Block Cipher)",
abstract = "In this paper a hardware implementation of a high throughput 128- bits Advanced Encryption Standard (AES) algorithm on a single chip of Xilinx Spartan III XC3S1000 FPGA has been presented. The bus width of the architecture is 32 bit. Pipelining method has been used in this design in order to achieve a higher speed. SubBytes method has been implemented using both composite field method and fixed Rom for further analysis and comparison of performance. Through a perfect combination of different methods of SBox and key Expansion, a notable speed has been achieved in the range of 1.11 Gbps to 3.22 Gbps. An in depth analysis became possible as the whole architecture was tested in four combination (composite field and Rom for both sub bytes and key expansion). All the methods have been discussed with a proper statistical analysis and performance charts.",
keywords = "AES, High throughput, MixColumn, Pipelining, SBox",
author = "Tanzilur Rahman and Shengyi Pan and Qi Zhang",
year = "2010",
language = "English",
isbn = "9789881701282",
series = "Proceedings of the International MultiConference of Engineers and Computer Scientists 2010, IMECS 2010",
pages = "1217--1221",
booktitle = "Proceedings of the International MultiConference of Engineers and Computer Scientists 2010, IMECS 2010",
note = "International MultiConference of Engineers and Computer Scientists 2010, IMECS 2010 ; Conference date: 17-03-2010 Through 19-03-2010",
}