Design and verification of DDR SDRAM memory controller using SystemVerilog for higher coverage

In present electronic systems, DDR SDRAM (Double Data Rate Synchronous Dynamic Random-AccessMemory) is an next level advanced version of regular SDRAM, and it was developed with advanced key features such as effective use of memory bandwidth and its capability to transact data on both edges of clock cycles. DDR SDRAM is widely used in computer applications like laptops, DSP processing systems and networking. Cost and speed are the two important factors in designing memories like DDR SDRAM which will meet the standards in the field of DSP applications. Because of its high speed, burst access and pipeline feature DDR SDRAM becomes more popular. The main basic operations of DDR SDRAM memory controller are very much common to that of SDR (Single Data Rate) SDRAM memory controller and they differ only in their circuit design. DDR simply use sophisticated circuit techniques to achieve high speed in order to perform a greater number of operations per clock cycles. DDR SDRAM uses double data rate architecture wherein DDR SDRAM (also known DDR1) means transaction of data on both the rising and falling edge of the clock cycles. The DDR SDRAM controller makes many lowlevel tasks invisible to the user like refresh, initialization and timings. DDR SDRAM also designed with objective of using proper commands like Read/Write accesses, proper active and pre-charge command etc. In this work a DDR SDRAM controller is designed using Verilog HDL and Verification is carried out using SystemVerilog by Questasim Tool. Functional coverage of 100% is achieved by applying randomized test cases.