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Design and Validation of Fault-Tolerant Boost Inverter Topology

  • Marif Daula Siddique
  • , Prasanth Sundararajan
  • , Mrutyunjaya Sahani
  • , Rahul Sadan
  • , Bhujade
  • , Kolantla Dharani
  • , Sanjib Kumar Panda

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

With the use of a high number of components in the multilevel converters, the chances of converter failure due to malfunction in components are high leading to reduced reliability and performance. In this paper, a new converter topology along with the fault-tolerant configuration which can be operated in two modes of operation has been proposed which incorporates the boosting feature as well. A detailed analysis for considering the faults in different switches for different modes of operation has been analyzed. Simulation results have been presented in this paper to show the performance and efficacy of the proposed topology.

Original languageEnglish
Title of host publication2024 IEEE International Communications Energy Conference, INTELEC 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350370577
DOIs
StatePublished - 2024

Publication series

NameINTELEC, International Telecommunications Energy Conference (Proceedings)
ISSN (Print)0275-0473

Bibliographical note

Publisher Copyright:
© 2024 IEEE.

Keywords

  • Boost converter
  • Fault-tolerant
  • Multilevel converter
  • SC-based topology

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering

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