Design and Optimization of Buffer Chains and Logic Circuits in a BiCMOS Environment

Muhammad S. Elrabaa; Mohamed I. Elmasry

doi:10.1109/4.133170

Design and Optimization of Buffer Chains and Logic Circuits in a BiCMOS Environment

Muhammad S. Elrabaa
, Mohamed I. Elmasry

Research output: Contribution to journal › Article › peer-review

7 Scopus citations

Abstract

In this work the design and optimization of Bi CMOS buffer chains and multilevel logic circuits are reported. BiCMOS speedup contours are introduced and analytical expressions for the delay are obtained. The speedup contours and the delay expressions were used in the design and optimization of BiCMOS buffer chains. Also, general design guidelines, which can be easily automated, for circuit design in a BiCMOS environment are given. Designing multistage mixed CMOS/BiCMOS buffers, BiCMOS complex logic gates, and multilevel CML gates is also studied and results are reported.

Original language	English
Pages (from-to)	792-801
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	27
Issue number	5
DOIs	https://doi.org/10.1109/4.133170
State	Published - May 1992
Externally published	Yes

Bibliographical note

Funding Information:
Manuscript received August 27, 1991; revised December 25. 1991. This work was supported in part by NSERC, ITRC, and MICRONET research grants. The authors are with the VLSI Research Group, Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ont., Canada N2L 3G1. IEEE Log Number 9106950.

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/4.133170

Cite this

@article{8f2f238efceb44e5880acc5e01341bd2,

title = "Design and Optimization of Buffer Chains and Logic Circuits in a BiCMOS Environment",

abstract = "In this work the design and optimization of Bi CMOS buffer chains and multilevel logic circuits are reported. BiCMOS speedup contours are introduced and analytical expressions for the delay are obtained. The speedup contours and the delay expressions were used in the design and optimization of BiCMOS buffer chains. Also, general design guidelines, which can be easily automated, for circuit design in a BiCMOS environment are given. Designing multistage mixed CMOS/BiCMOS buffers, BiCMOS complex logic gates, and multilevel CML gates is also studied and results are reported.",

author = "Elrabaa, \{Muhammad S.\} and Elmasry, \{Mohamed I.\}",

note = "Funding Information: Manuscript received August 27, 1991; revised December 25. 1991. This work was supported in part by NSERC, ITRC, and MICRONET research grants. The authors are with the VLSI Research Group, Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ont., Canada N2L 3G1. IEEE Log Number 9106950.",

year = "1992",

month = may,

doi = "10.1109/4.133170",

language = "English",

volume = "27",

pages = "792--801",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - Design and Optimization of Buffer Chains and Logic Circuits in a BiCMOS Environment

AU - Elrabaa, Muhammad S.

AU - Elmasry, Mohamed I.

N1 - Funding Information: Manuscript received August 27, 1991; revised December 25. 1991. This work was supported in part by NSERC, ITRC, and MICRONET research grants. The authors are with the VLSI Research Group, Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ont., Canada N2L 3G1. IEEE Log Number 9106950.

PY - 1992/5

Y1 - 1992/5

N2 - In this work the design and optimization of Bi CMOS buffer chains and multilevel logic circuits are reported. BiCMOS speedup contours are introduced and analytical expressions for the delay are obtained. The speedup contours and the delay expressions were used in the design and optimization of BiCMOS buffer chains. Also, general design guidelines, which can be easily automated, for circuit design in a BiCMOS environment are given. Designing multistage mixed CMOS/BiCMOS buffers, BiCMOS complex logic gates, and multilevel CML gates is also studied and results are reported.

AB - In this work the design and optimization of Bi CMOS buffer chains and multilevel logic circuits are reported. BiCMOS speedup contours are introduced and analytical expressions for the delay are obtained. The speedup contours and the delay expressions were used in the design and optimization of BiCMOS buffer chains. Also, general design guidelines, which can be easily automated, for circuit design in a BiCMOS environment are given. Designing multistage mixed CMOS/BiCMOS buffers, BiCMOS complex logic gates, and multilevel CML gates is also studied and results are reported.

UR - https://www.scopus.com/pages/publications/0026866287

U2 - 10.1109/4.133170

DO - 10.1109/4.133170

M3 - Article

AN - SCOPUS:0026866287

SN - 0018-9200

VL - 27

SP - 792

EP - 801

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 5

ER -

Design and Optimization of Buffer Chains and Logic Circuits in a BiCMOS Environment

Abstract

Bibliographical note

ASJC Scopus subject areas

Access to Document

Fingerprint

Cite this