Abstract
This paper presents a newly designed fault-ride-through (FRT) scheme i.e. bridge-type fault-current limiter (BFCL) for Grid-Tied photovoltaic system (PVS) to optimize unbalance fault variables. A 100 kW three-phase Grid-Tied MATLAB/Simulink model is used to analyze the system response during unbalance conditions. The simulation results of designed FRT scheme are critically compared with conventionally adopted FRT scheme i.e. crowbar circuitry. However, for inverter control proportional integrator (PI) controller is used. Moreover, the analysis is carried out for faults at point of common-coupling (PCC) as well as 5-km away from PCC. The obtained simulated results of PI controller with well-designed FRT scheme authenticates stable, minimum oscillation, ripples free, robust and fast performance for unbalance fault variables as compared to previous work.
Original language | English |
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Title of host publication | 15th International Conference on Emerging Technologies, ICET 2019 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781728154039 |
DOIs | |
State | Published - Dec 2019 |
Externally published | Yes |
Publication series
Name | 15th International Conference on Emerging Technologies, ICET 2019 |
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Bibliographical note
Publisher Copyright:© 2019 IEEE.
Keywords
- BFCL scheme
- FRT scheme
- Grid- Tied PV system
- LVRT capability
- PI controller
ASJC Scopus subject areas
- Computer Networks and Communications
- Hardware and Architecture
- Electrical and Electronic Engineering
- Control and Optimization
- Health Informatics
- Instrumentation