Design and analysis of multicore matrix multiplier for image processing

Farouq Aliyu, Shuaib Mohammed, Alaeddin Amin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The need faster processing speed is in demand lately. Parallel computing and compound instructions are some of the techniques that have been employed by scientists so far. In this paper, a high-performance multi-core matrix multiplier using parallel computing techniques has been designed and implemented. Simulation results are promising and indicate that the area and power consumed by the proposed matrix multiplier increase linearly with the number of processors and latency was found to decrease by a factor of $\frac{1}{p}$ where $p$ is the number of processors. Due to its salient features, the proposed multicore multiplier can be utilized to improve processing speeds in graphical processor units.

Original languageEnglish
Title of host publication2019 International Conference on Innovation and Intelligence for Informatics, Computing, and Technologies, 3ICT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728130125
DOIs
StatePublished - Sep 2019

Publication series

Name2019 International Conference on Innovation and Intelligence for Informatics, Computing, and Technologies, 3ICT 2019

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

Keywords

  • Computer Arithmetic
  • Matrix Multiplication
  • Multicore Systems
  • Parallel Computing
  • Synthesis
  • VHDL

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Networks and Communications
  • Computer Science Applications
  • Hardware and Architecture
  • Information Systems
  • Health Informatics

Fingerprint

Dive into the research topics of 'Design and analysis of multicore matrix multiplier for image processing'. Together they form a unique fingerprint.

Cite this