Abstract
The need faster processing speed is in demand lately. Parallel computing and compound instructions are some of the techniques that have been employed by scientists so far. In this paper, a high-performance multi-core matrix multiplier using parallel computing techniques has been designed and implemented. Simulation results are promising and indicate that the area and power consumed by the proposed matrix multiplier increase linearly with the number of processors and latency was found to decrease by a factor of $\frac{1}{p}$ where $p$ is the number of processors. Due to its salient features, the proposed multicore multiplier can be utilized to improve processing speeds in graphical processor units.
| Original language | English |
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| Title of host publication | 2019 International Conference on Innovation and Intelligence for Informatics, Computing, and Technologies, 3ICT 2019 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781728130125 |
| DOIs | |
| State | Published - Sep 2019 |
Publication series
| Name | 2019 International Conference on Innovation and Intelligence for Informatics, Computing, and Technologies, 3ICT 2019 |
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Bibliographical note
Publisher Copyright:© 2019 IEEE.
Keywords
- Computer Arithmetic
- Matrix Multiplication
- Multicore Systems
- Parallel Computing
- Synthesis
- VHDL
ASJC Scopus subject areas
- Artificial Intelligence
- Computer Networks and Communications
- Computer Science Applications
- Hardware and Architecture
- Information Systems
- Health Informatics