Abstract
In this paper, we study the testability preservation of the concurrent decomposition and factorization transformations under several delay-fault testing constraints. We show that all transformations, except dual extraction of multiplexor structures, preserve testability with respect to a general Robust Path-Delay-Fault (RPDF) test set, Validatable Nonrobust (VNR) delay-fault test set, and Delay Verification (DV) test set. In addition, we provide new, sufficient conditions for the algebraic resubstitution with complement transformation to preserve RPDF, VNR,and DV testability, that cover a larger class of complementary expressions than was known previously. Experimental results on a set of Berkeley PLA's and MCNC benchmark circuits show that dual extraction of multiplexor structures is utilized in only 2 out of 50 benchmark circuits. We demonstrate that while disabling this transformation has negligible effect on area, it results in an efficient test-set preserving multilevel logic synthesis algorithm, that preserves testability with respect to RPDF, VNR, and DV test sets.
| Original language | English |
|---|---|
| Pages (from-to) | 582-590 |
| Number of pages | 9 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 14 |
| Issue number | 5 |
| DOIs | |
| State | Published - May 1995 |
| Externally published | Yes |
Bibliographical note
Funding Information:Manuscript received September 11, 1994; revised January 25, 1995. This work was supported by Cooperative Research and Development Grant from the National Sciences and Engineering Research Council of Canada and BNR, and a scholarship from the Quebec Fonds pour la Formation de Chercheurs et 1’Aide h la Recherche. This paper was recommended by Guest Editors W. Maly and Y. zorian.
ASJC Scopus subject areas
- Software
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering