TY - GEN
T1 - Defect tolerance in nanotechnology switches using a greedy reconfiguration algorithm
AU - Ramsundar, S.
AU - Al-Yamani, Ahmad
AU - Pradhan, Dhiraj K.
PY - 2007
Y1 - 2007
N2 - Lithography based IC fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires. Such a process is subject to a high defect rate, which can be tolerated using carefully crafted defect tolerance techniques. This paper presents an algorithm for reconfiguration-based defect tolerance in nanotechnology switches. The algorithm offers an average switch density improvement of 50% to 100% to most recently published techniques.1
AB - Lithography based IC fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires. Such a process is subject to a high defect rate, which can be tolerated using carefully crafted defect tolerance techniques. This paper presents an algorithm for reconfiguration-based defect tolerance in nanotechnology switches. The algorithm offers an average switch density improvement of 50% to 100% to most recently published techniques.1
UR - https://www.scopus.com/pages/publications/34548120799
U2 - 10.1109/ISQED.2007.55
DO - 10.1109/ISQED.2007.55
M3 - Conference contribution
AN - SCOPUS:34548120799
SN - 0769527957
SN - 9780769527956
T3 - Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007
SP - 807
EP - 813
BT - Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007
ER -