Abstract
In this work, we present DE-ZFP: a hardware implementation of modified ZFP compression and decompression algorithms on a Field Programmable Gate Array (FPGA). It can be used to accelerate applications running on a host CPU that generates large volumes of floating point data. The proposed design uses dictionary-based encoding (DE) in lieu of ZFP's original embedded encoding to maximize hardware performance. Furthermore, the block encoder logic was optimized such that the loss of compression efficiency due to DE remains within 4%–13% of the original ZFP software implementation, with up to 19x improvement in throughput.
Original language | English |
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Article number | 104453 |
Journal | Microprocessors and Microsystems |
Volume | 90 |
DOIs | |
State | Published - Apr 2022 |
Bibliographical note
Funding Information:This research was funded by KFUPM under project No. DF191015 .
Funding Information:
This research was funded by KFUPM under project No. DF191015.This work is supported by King Fahd University of Petroleum & Minerals under project No. DF191015. The authors acknowledge the help of Dr. Peter Lindstrom. Hurricane Isabel data produced by the Weather Research and Forecast model, courtesy of NCAR and the U.S. National Science Foundation. Data collection is a courtesy of DOE NNSA ECP project and the ECP CODAR project.
Funding Information:
This work is supported by King Fahd University of Petroleum & Minerals under project No. DF191015. The authors acknowledge the help of Dr. Peter Lindstrom. Hurricane Isabel data produced by the Weather Research and Forecast model, courtesy of NCAR and the U.S. National Science Foundation. Data collection is a courtesy of DOE NNSA ECP project and the ECP CODAR project.
Publisher Copyright:
© 2022 Elsevier B.V.
Keywords
- FPGA acceleration
- Hardware implementation
- Lossy compression
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Computer Networks and Communications
- Artificial Intelligence