DE-ZFP: An FPGA implementation of a modified ZFP compression/decompression algorithm

Mahmoud Habboush, Aiman H. El-Maleh*, Muhammad E.S. Elrabaa, Saleh AlSaleh

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

In this work, we present DE-ZFP: a hardware implementation of modified ZFP compression and decompression algorithms on a Field Programmable Gate Array (FPGA). It can be used to accelerate applications running on a host CPU that generates large volumes of floating point data. The proposed design uses dictionary-based encoding (DE) in lieu of ZFP's original embedded encoding to maximize hardware performance. Furthermore, the block encoder logic was optimized such that the loss of compression efficiency due to DE remains within 4%–13% of the original ZFP software implementation, with up to 19x improvement in throughput.

Original languageEnglish
Article number104453
JournalMicroprocessors and Microsystems
Volume90
DOIs
StatePublished - Apr 2022

Bibliographical note

Publisher Copyright:
© 2022 Elsevier B.V.

Keywords

  • FPGA acceleration
  • Hardware implementation
  • Lossy compression

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence

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