Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors

Jing Kai Huang; Yi Wan; Junjie Shi; Ji Zhang; Zeheng Wang; Zi Liang Yang; Bo Chao Huang; Ya Ping Chiu; Wenxuan Wang; Ni Yang; Yang Liu; Chun Ho Lin; Xinwei Guan; Long Hu; Jack Yang; Danyang Wang; Vincent Tung; Kourosh Kalantar-Zadeh; Tom Wu; Xiaotao Zu; Liang Qiao; Sean Li; Lain Jong Li

doi:10.1109/IEDM45625.2022.10019466

Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors

Jing Kai Huang^*
, Yi Wan
, Junjie Shi
, Ji Zhang
, Zeheng Wang
, Zi Liang Yang
, Bo Chao Huang
, Ya Ping Chiu
, Wenxuan Wang
, Ni Yang
, Yang Liu
, Chun Ho Lin
, Xinwei Guan
, Long Hu
, Jack Yang
, Danyang Wang
, Vincent Tung
, Kourosh Kalantar-Zadeh
, Tom Wu
, Xiaotao Zu

Liang Qiao, Sean Li, Lain Jong Li

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

Atomically thin 2D semiconductors have been regarded as promising candidates for the channels in ultra-scaled transistors. Although high-performance 2D field-effect transistors (FETs) have been demonstrated, the integration with conventional high-κ gate insulators is yet to be improved for energy-efficient devices. Here, 2D FETs with sub-1 nm capacitance equivalent thickness (CET) are demonstrated through the integration of transferrable single-crystal SrTiO3 thin dielectrics with a monolayer CVD MoS2, where the optimized SrTiO3 gate stack exhibits a gate leakage far below the low-standby-power limit (1.5×10-2 A/cm2). The short-channel devices manifest good reliability and competitive performance characteristics, including the steep subthreshold swing (SS) down to 75 mV dec-1 and a large ON/OFF current ratio of 106.

Original language	English
Title of host publication	2022 International Electron Devices Meeting, IEDM 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	761-764
Number of pages	4
ISBN (Electronic)	9781665489591
DOIs	https://doi.org/10.1109/IEDM45625.2022.10019466
State	Published - 2022
Externally published	Yes
Event	2022 International Electron Devices Meeting, IEDM 2022 - San Francisco, United States Duration: 3 Dec 2022 → 7 Dec 2022

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2022-December
ISSN (Print)	0163-1918

Conference

Conference	2022 International Electron Devices Meeting, IEDM 2022
Country/Territory	United States
City	San Francisco
Period	3/12/22 → 7/12/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1109/IEDM45625.2022.10019466

Cite this

Huang, J. K., Wan, Y., Shi, J., Zhang, J., Wang, Z., Yang, Z. L., Huang, B. C., Chiu, Y. P., Wang, W., Yang, N., Liu, Y., Lin, C. H., Guan, X., Hu, L., Yang, J., Wang, D., Tung, V., Kalantar-Zadeh, K., Wu, T., ... Li, L. J. (2022). Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors. In 2022 International Electron Devices Meeting, IEDM 2022 (pp. 761-764). (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2022-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM45625.2022.10019466

@inproceedings{ab6295ba43c8493aabfc1fa3b468e630,

title = "Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors",

abstract = "Atomically thin 2D semiconductors have been regarded as promising candidates for the channels in ultra-scaled transistors. Although high-performance 2D field-effect transistors (FETs) have been demonstrated, the integration with conventional high-κ gate insulators is yet to be improved for energy-efficient devices. Here, 2D FETs with sub-1 nm capacitance equivalent thickness (CET) are demonstrated through the integration of transferrable single-crystal SrTiO3 thin dielectrics with a monolayer CVD MoS2, where the optimized SrTiO3 gate stack exhibits a gate leakage far below the low-standby-power limit (1.5{\texttimes}10-2 A/cm2). The short-channel devices manifest good reliability and competitive performance characteristics, including the steep subthreshold swing (SS) down to 75 mV dec-1 and a large ON/OFF current ratio of 106.",

author = "Huang, \{Jing Kai\} and Yi Wan and Junjie Shi and Ji Zhang and Zeheng Wang and Yang, \{Zi Liang\} and Huang, \{Bo Chao\} and Chiu, \{Ya Ping\} and Wenxuan Wang and Ni Yang and Yang Liu and Lin, \{Chun Ho\} and Xinwei Guan and Long Hu and Jack Yang and Danyang Wang and Vincent Tung and Kourosh Kalantar-Zadeh and Tom Wu and Xiaotao Zu and Liang Qiao and Sean Li and Li, \{Lain Jong\}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 International Electron Devices Meeting, IEDM 2022 ; Conference date: 03-12-2022 Through 07-12-2022",

year = "2022",

doi = "10.1109/IEDM45625.2022.10019466",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "761--764",

booktitle = "2022 International Electron Devices Meeting, IEDM 2022",

address = "United States",

}

Huang, JK, Wan, Y, Shi, J, Zhang, J, Wang, Z, Yang, ZL, Huang, BC, Chiu, YP, Wang, W, Yang, N, Liu, Y, Lin, CH, Guan, X, Hu, L, Yang, J, Wang, D, Tung, V, Kalantar-Zadeh, K, Wu, T, Zu, X, Qiao, L, Li, S & Li, LJ 2022, Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors. in 2022 International Electron Devices Meeting, IEDM 2022. Technical Digest - International Electron Devices Meeting, IEDM, vol. 2022-December, Institute of Electrical and Electronics Engineers Inc., pp. 761-764, 2022 International Electron Devices Meeting, IEDM 2022, San Francisco, United States, 3/12/22. https://doi.org/10.1109/IEDM45625.2022.10019466

Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors. / Huang, Jing Kai; Wan, Yi; Shi, Junjie et al.
2022 International Electron Devices Meeting, IEDM 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 761-764 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2022-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Crystalline Complex Oxide Membrane

T2 - 2022 International Electron Devices Meeting, IEDM 2022

AU - Huang, Jing Kai

AU - Wan, Yi

AU - Shi, Junjie

AU - Zhang, Ji

AU - Wang, Zeheng

AU - Yang, Zi Liang

AU - Huang, Bo Chao

AU - Chiu, Ya Ping

AU - Wang, Wenxuan

AU - Yang, Ni

AU - Liu, Yang

AU - Lin, Chun Ho

AU - Guan, Xinwei

AU - Hu, Long

AU - Yang, Jack

AU - Wang, Danyang

AU - Tung, Vincent

AU - Kalantar-Zadeh, Kourosh

AU - Wu, Tom

AU - Zu, Xiaotao

AU - Qiao, Liang

AU - Li, Sean

AU - Li, Lain Jong

PY - 2022

Y1 - 2022

N2 - Atomically thin 2D semiconductors have been regarded as promising candidates for the channels in ultra-scaled transistors. Although high-performance 2D field-effect transistors (FETs) have been demonstrated, the integration with conventional high-κ gate insulators is yet to be improved for energy-efficient devices. Here, 2D FETs with sub-1 nm capacitance equivalent thickness (CET) are demonstrated through the integration of transferrable single-crystal SrTiO3 thin dielectrics with a monolayer CVD MoS2, where the optimized SrTiO3 gate stack exhibits a gate leakage far below the low-standby-power limit (1.5×10-2 A/cm2). The short-channel devices manifest good reliability and competitive performance characteristics, including the steep subthreshold swing (SS) down to 75 mV dec-1 and a large ON/OFF current ratio of 106.

AB - Atomically thin 2D semiconductors have been regarded as promising candidates for the channels in ultra-scaled transistors. Although high-performance 2D field-effect transistors (FETs) have been demonstrated, the integration with conventional high-κ gate insulators is yet to be improved for energy-efficient devices. Here, 2D FETs with sub-1 nm capacitance equivalent thickness (CET) are demonstrated through the integration of transferrable single-crystal SrTiO3 thin dielectrics with a monolayer CVD MoS2, where the optimized SrTiO3 gate stack exhibits a gate leakage far below the low-standby-power limit (1.5×10-2 A/cm2). The short-channel devices manifest good reliability and competitive performance characteristics, including the steep subthreshold swing (SS) down to 75 mV dec-1 and a large ON/OFF current ratio of 106.

UR - https://www.scopus.com/pages/publications/85147505158

U2 - 10.1109/IEDM45625.2022.10019466

DO - 10.1109/IEDM45625.2022.10019466

M3 - Conference contribution

AN - SCOPUS:85147505158

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 761

EP - 764

BT - 2022 International Electron Devices Meeting, IEDM 2022

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 3 December 2022 through 7 December 2022

ER -

Huang JK, Wan Y, Shi J, Zhang J, Wang Z, Yang ZL et al. Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors. In 2022 International Electron Devices Meeting, IEDM 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 761-764. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM45625.2022.10019466

Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors

Abstract

Publication series

Conference

Bibliographical note

UN SDGs

ASJC Scopus subject areas

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