Compiler transformation to improve memory access time in SIMD systems

The serialization of memory accesses and network conflicts are two major limiting factors in lock-step parallel memories. We derive conditions for accessing parallel memories which is free of both network and memory conflicts. This applies to accessing arbitrary sets of linear data patterns. We also combine different access patterns (NP-complete) into one single compiler address transformation. The synthesized storage scheme applies to arbitrary linear patterns, arbitrary multistage networks, and arbitrary number of power-of-2 memories. We propose a new heuristic for synthesizing combined XOR-matrices. Performance of optimized storage schemes is presented for sorting and for combining arbitrary sets of power-of-2 patterns.