Abstract
Analysis of the tradeoff between hardware overhead, runtime and test data volume is presented when implementing systematic scan reconfiguration using centralised and distributed architectures of the segmented addressable scan, which is an Illinois-scan-based architecture. The results show that the centralised scheme offers better data volume compression, similar automatic test pattern generation (ATPG) runtime results and lower hardware overhead. The cost with the centralised scheme is in the routing congestion.
| Original language | English |
|---|---|
| Pages (from-to) | 108-117 |
| Number of pages | 10 |
| Journal | IET Computers and Digital Techniques |
| Volume | 2 |
| Issue number | 2 |
| DOIs | |
| State | Published - 2008 |
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering