Abstract
In this paper, a clock jitter correction circuit is proposed. The circuit corrects the jitter error in the location of the rising and falling edges of the clock pulses. The circuit topology employs delay units and time selection window to ensure jitter free output. The number of the corrected edges of the clock signal is equal to the number of edge correction units.
| Original language | English |
|---|---|
| Title of host publication | 2016 16th Mediterranean Microwave Symposium, MMS 2016 |
| Publisher | IEEE Computer Society |
| ISBN (Electronic) | 9781509025862 |
| DOIs | |
| State | Published - 2 Jul 2016 |
| Externally published | Yes |
Publication series
| Name | Mediterranean Microwave Symposium |
|---|---|
| Volume | 0 |
| ISSN (Print) | 2157-9822 |
| ISSN (Electronic) | 2157-9830 |
Bibliographical note
Publisher Copyright:© 2016 IEEE.
Keywords
- Clock Jitter Correction
- Clock signal distribution
- Wireless clock distribution
ASJC Scopus subject areas
- Electrical and Electronic Engineering