Clock jitter correction circuit for high speed clock signals using delay units a nd time selection window

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, a clock jitter correction circuit is proposed. The circuit corrects the jitter error in the location of the rising and falling edges of the clock pulses. The circuit topology employs delay units and time selection window to ensure jitter free output. The number of the corrected edges of the clock signal is equal to the number of edge correction units.

Original languageEnglish
Title of host publication2016 16th Mediterranean Microwave Symposium, MMS 2016
PublisherIEEE Computer Society
ISBN (Electronic)9781509025862
DOIs
StatePublished - 2 Jul 2016
Externally publishedYes

Publication series

NameMediterranean Microwave Symposium
Volume0
ISSN (Print)2157-9822
ISSN (Electronic)2157-9830

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Keywords

  • Clock Jitter Correction
  • Clock signal distribution
  • Wireless clock distribution

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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