Charge Pump based Phase Locked Loop with Transmission Gate using Combinational Phase Frequency Detector

K. Sharanya; V. Vignesh; Sreeja Kochuvila; Navin Kumar; Mufti Mahmud

doi:10.1109/CONECCT62155.2024.10677259

Charge Pump based Phase Locked Loop with Transmission Gate using Combinational Phase Frequency Detector

K. Sharanya
, V. Vignesh
, Sreeja Kochuvila
, Navin Kumar^*
, Mufti Mahmud

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This work describes the design of a charge pump-based phase locked loop (PLL). Design is carried out using 45nm CMOS process targeted at sub-6GHz frequency range. Candence virtuoso studio is used to design the circuit. It uses a combinational circuit phase detector with transmission gates that resolves the issues of blind zone and dead zone, along with a three-stage current starved voltage-controlled oscillator (VCO). The proposed frequency synthesizer operates with a very low power dissipation of 8.05 mW from a 0.75V power supply, frequency of VCO centered at 2.5GHz, with a phase noise performance of - 127 dBc/Hz at 1 MHz offset. It is intended to achieve phase locking in the sub 6GHz frequency range for use in software defined radio (SDR) and exhibits reduced lock time of ~13.5ns, offering a percentage improvement of 32.5%.

Original language	English
Title of host publication	Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350385922
DOIs	https://doi.org/10.1109/CONECCT62155.2024.10677259
State	Published - 2024
Externally published	Yes
Event	10th IEEE International Conference on Electronics, Computing and Communication Technologies, CONECCT 2024 - Bangalore, India Duration: 12 Jul 2024 → 14 Jul 2024

Publication series

Name	Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies

Conference

Conference	10th IEEE International Conference on Electronics, Computing and Communication Technologies, CONECCT 2024
Country/Territory	India
City	Bangalore
Period	12/07/24 → 14/07/24

Bibliographical note

Publisher Copyright:
© 2024 IEEE.

Keywords

Charge pump
PLL
Transmission gate
combinational phase detector
current starved VCO

ASJC Scopus subject areas

Control and Optimization
Instrumentation
Artificial Intelligence
Computer Networks and Communications
Computer Science Applications
Information Systems and Management
Electrical and Electronic Engineering

Access to Document

10.1109/CONECCT62155.2024.10677259

Cite this

Sharanya, K., Vignesh, V., Kochuvila, S., Kumar, N., & Mahmud, M. (2024). Charge Pump based Phase Locked Loop with Transmission Gate using Combinational Phase Frequency Detector. In Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies (Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CONECCT62155.2024.10677259

Sharanya, K. ; Vignesh, V. ; Kochuvila, Sreeja et al. / Charge Pump based Phase Locked Loop with Transmission Gate using Combinational Phase Frequency Detector. Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies. Institute of Electrical and Electronics Engineers Inc., 2024. (Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies).

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title = "Charge Pump based Phase Locked Loop with Transmission Gate using Combinational Phase Frequency Detector",

abstract = "This work describes the design of a charge pump-based phase locked loop (PLL). Design is carried out using 45nm CMOS process targeted at sub-6GHz frequency range. Candence virtuoso studio is used to design the circuit. It uses a combinational circuit phase detector with transmission gates that resolves the issues of blind zone and dead zone, along with a three-stage current starved voltage-controlled oscillator (VCO). The proposed frequency synthesizer operates with a very low power dissipation of 8.05 mW from a 0.75V power supply, frequency of VCO centered at 2.5GHz, with a phase noise performance of - 127 dBc/Hz at 1 MHz offset. It is intended to achieve phase locking in the sub 6GHz frequency range for use in software defined radio (SDR) and exhibits reduced lock time of \textasciitilde{}13.5ns, offering a percentage improvement of 32.5\%.",

keywords = "Charge pump, PLL, Transmission gate, combinational phase detector, current starved VCO",

author = "K. Sharanya and V. Vignesh and Sreeja Kochuvila and Navin Kumar and Mufti Mahmud",

note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 10th IEEE International Conference on Electronics, Computing and Communication Technologies, CONECCT 2024 ; Conference date: 12-07-2024 Through 14-07-2024",

year = "2024",

doi = "10.1109/CONECCT62155.2024.10677259",

language = "English",

series = "Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Sharanya, K, Vignesh, V, Kochuvila, S, Kumar, N & Mahmud, M 2024, Charge Pump based Phase Locked Loop with Transmission Gate using Combinational Phase Frequency Detector. in Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies. Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies, Institute of Electrical and Electronics Engineers Inc., 10th IEEE International Conference on Electronics, Computing and Communication Technologies, CONECCT 2024, Bangalore, India, 12/07/24. https://doi.org/10.1109/CONECCT62155.2024.10677259

Charge Pump based Phase Locked Loop with Transmission Gate using Combinational Phase Frequency Detector. / Sharanya, K.; Vignesh, V.; Kochuvila, Sreeja et al.
Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies. Institute of Electrical and Electronics Engineers Inc., 2024. (Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Charge Pump based Phase Locked Loop with Transmission Gate using Combinational Phase Frequency Detector

AU - Sharanya, K.

AU - Vignesh, V.

AU - Kochuvila, Sreeja

AU - Kumar, Navin

AU - Mahmud, Mufti

PY - 2024

Y1 - 2024

N2 - This work describes the design of a charge pump-based phase locked loop (PLL). Design is carried out using 45nm CMOS process targeted at sub-6GHz frequency range. Candence virtuoso studio is used to design the circuit. It uses a combinational circuit phase detector with transmission gates that resolves the issues of blind zone and dead zone, along with a three-stage current starved voltage-controlled oscillator (VCO). The proposed frequency synthesizer operates with a very low power dissipation of 8.05 mW from a 0.75V power supply, frequency of VCO centered at 2.5GHz, with a phase noise performance of - 127 dBc/Hz at 1 MHz offset. It is intended to achieve phase locking in the sub 6GHz frequency range for use in software defined radio (SDR) and exhibits reduced lock time of ~13.5ns, offering a percentage improvement of 32.5%.

AB - This work describes the design of a charge pump-based phase locked loop (PLL). Design is carried out using 45nm CMOS process targeted at sub-6GHz frequency range. Candence virtuoso studio is used to design the circuit. It uses a combinational circuit phase detector with transmission gates that resolves the issues of blind zone and dead zone, along with a three-stage current starved voltage-controlled oscillator (VCO). The proposed frequency synthesizer operates with a very low power dissipation of 8.05 mW from a 0.75V power supply, frequency of VCO centered at 2.5GHz, with a phase noise performance of - 127 dBc/Hz at 1 MHz offset. It is intended to achieve phase locking in the sub 6GHz frequency range for use in software defined radio (SDR) and exhibits reduced lock time of ~13.5ns, offering a percentage improvement of 32.5%.

KW - Charge pump

KW - PLL

KW - Transmission gate

KW - combinational phase detector

KW - current starved VCO

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U2 - 10.1109/CONECCT62155.2024.10677259

DO - 10.1109/CONECCT62155.2024.10677259

M3 - Conference contribution

AN - SCOPUS:85205781746

T3 - Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies

BT - Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies, CONECCT 2024

Y2 - 12 July 2024 through 14 July 2024

ER -

Sharanya K, Vignesh V, Kochuvila S, Kumar N, Mahmud M. Charge Pump based Phase Locked Loop with Transmission Gate using Combinational Phase Frequency Detector. In Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies. Institute of Electrical and Electronics Engineers Inc. 2024. (Proceedings of CONECCT 2024 - 10th IEEE International Conference on Electronics, Computing and Communication Technologies). doi: 10.1109/CONECCT62155.2024.10677259

Charge Pump based Phase Locked Loop with Transmission Gate using Combinational Phase Frequency Detector

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this