Cells reconfiguration around defects in CMOS/nanofabric circuits using simulated evolution heuristic

Recent advances in nanoscale components assembly have led to the invention of low-power and high-density nanofabrics, which can be integrated with conventional CMOS transistors. CMOS/nanofabric hybrid circuits combine the flexibility and high fabrication yield advantages of CMOS technology with ultra fast nanometer-scale devices. CMOL is a novel architecture which consists of a nanofabric overlay on top of a CMOS stack. CMOL can be configured to implement NOR-based logic circuits by programming nanodevices placed between the nanofabric's overlapping nanowires. Defects rate in nanofabric-based circuits is expected to be higher than that of conventional CMOS technology. Misassembly of nanodevices will lead to non-programmable crosspoints, while broken nanowires will result in unreachable circuit's components. In such cases, utilizing CMOS/nanofabric architectures requires robust reconfiguration-based defect-tolerance design automation tools that can circumvent defective components and insure circuits functionality. In this work, we propose a heuristic-based nanofabric reconfiguration around defective nano-components in CMOL circuits. Simulated Evolution (SimE) is formulated to find circuits configurations that adhere to nanowires connectivity constraint and rely on non defective components. Circuits of various sizes from ISCAS'89 benchmarks were used to evaluate our proposed design. Results show that SimE yield successful reconfigurations in acceptable computation time when up to 50% of nanodevices are stuck-at-open and 70% of nanowires are broken.