CAT platform for analogue and mixed-signal test evaluation and optimization

Ahcéne Bounceur; Salvador Mir; Luis Rolìndez; Emmanuel Simeu

doi:10.1007/978-0-387-74909-9_16

CAT platform for analogue and mixed-signal test evaluation and optimization

Ahcéne Bounceur^*
, Salvador Mir
, Luis Rolìndez
, Emmanuel Simeu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

This paper introduces a Computer-Aided-Test platform that has been developed for the evaluation of test techniques for analogue and mixed-signal circuits. The CAT platform, integrated in the Cadence Design Framework Environment, includes tools for fault simulation, test generation and test optimization for these types of circuits. Fault modeling and fault injection are simulator independent, which makes this approach flexible with respect to past approaches. In this paper, the use of this platform is illustrated for test optimization for the case of a fully differential amplifier. Test limits are set using a statistical circuit performance analysis that accounts for process deviations, as a trade-off between estimated test metrics at the design stage. Specification-based tests are next optimized in terms of their capability of detecting catastrophic and parametric faults.

Original language	English
Title of host publication	VLSI-SoC
Subtitle of host publication	Research Trends in VLSI and Systems on Chip: Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France
Editors	Giovanni De Micheli, Salvador Mir, Ricardo Reis
Pages	281-300
Number of pages	20
DOIs	https://doi.org/10.1007/978-0-387-74909-9_16
State	Published - 2008
Externally published	Yes

Publication series

Name	IFIP International Federation for Information Processing
Volume	249
ISSN (Print)	1571-5736

ASJC Scopus subject areas

Information Systems and Management

Access to Document

10.1007/978-0-387-74909-9_16

Cite this

Bounceur, A., Mir, S., Rolìndez, L., & Simeu, E. (2008). CAT platform for analogue and mixed-signal test evaluation and optimization. In G. De Micheli, S. Mir, & R. Reis (Eds.), VLSI-SoC: Research Trends in VLSI and Systems on Chip: Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France (pp. 281-300). (IFIP International Federation for Information Processing; Vol. 249). https://doi.org/10.1007/978-0-387-74909-9_16

Bounceur, Ahcéne ; Mir, Salvador ; Rolìndez, Luis et al. / CAT platform for analogue and mixed-signal test evaluation and optimization. VLSI-SoC: Research Trends in VLSI and Systems on Chip: Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France. editor / Giovanni De Micheli ; Salvador Mir ; Ricardo Reis. 2008. pp. 281-300 (IFIP International Federation for Information Processing).

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title = "CAT platform for analogue and mixed-signal test evaluation and optimization",

abstract = "This paper introduces a Computer-Aided-Test platform that has been developed for the evaluation of test techniques for analogue and mixed-signal circuits. The CAT platform, integrated in the Cadence Design Framework Environment, includes tools for fault simulation, test generation and test optimization for these types of circuits. Fault modeling and fault injection are simulator independent, which makes this approach flexible with respect to past approaches. In this paper, the use of this platform is illustrated for test optimization for the case of a fully differential amplifier. Test limits are set using a statistical circuit performance analysis that accounts for process deviations, as a trade-off between estimated test metrics at the design stage. Specification-based tests are next optimized in terms of their capability of detecting catastrophic and parametric faults.",

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language = "English",

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Bounceur, A, Mir, S, Rolìndez, L & Simeu, E 2008, CAT platform for analogue and mixed-signal test evaluation and optimization. in G De Micheli, S Mir & R Reis (eds), VLSI-SoC: Research Trends in VLSI and Systems on Chip: Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France. IFIP International Federation for Information Processing, vol. 249, pp. 281-300. https://doi.org/10.1007/978-0-387-74909-9_16

CAT platform for analogue and mixed-signal test evaluation and optimization. / Bounceur, Ahcéne; Mir, Salvador; Rolìndez, Luis et al.
VLSI-SoC: Research Trends in VLSI and Systems on Chip: Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France. ed. / Giovanni De Micheli; Salvador Mir; Ricardo Reis. 2008. p. 281-300 (IFIP International Federation for Information Processing; Vol. 249).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper introduces a Computer-Aided-Test platform that has been developed for the evaluation of test techniques for analogue and mixed-signal circuits. The CAT platform, integrated in the Cadence Design Framework Environment, includes tools for fault simulation, test generation and test optimization for these types of circuits. Fault modeling and fault injection are simulator independent, which makes this approach flexible with respect to past approaches. In this paper, the use of this platform is illustrated for test optimization for the case of a fully differential amplifier. Test limits are set using a statistical circuit performance analysis that accounts for process deviations, as a trade-off between estimated test metrics at the design stage. Specification-based tests are next optimized in terms of their capability of detecting catastrophic and parametric faults.

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Bounceur A, Mir S, Rolìndez L, Simeu E. CAT platform for analogue and mixed-signal test evaluation and optimization. In De Micheli G, Mir S, Reis R, editors, VLSI-SoC: Research Trends in VLSI and Systems on Chip: Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France. 2008. p. 281-300. (IFIP International Federation for Information Processing). doi: 10.1007/978-0-387-74909-9_16

CAT platform for analogue and mixed-signal test evaluation and optimization

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