TY - GEN
T1 - CAT platform for analogue and mixed-signal test evaluation and optimization
AU - Bounceur, Ahcène
AU - Mir, Salvador
AU - Rolíndez, Luis
AU - Simeu, Emmanuel
PY - 2006
Y1 - 2006
N2 - This paper introduces a Computer-Aided-Test platform that has been developed for the evaluation of test techniques for analogue and mixed-signal circuits. The CAT platform, integrated in the Cadence Design Framework Environment, includes tools for fault simulation, test generation and test optimization for these types of circuits. Fault modeling and fault injection are simulator independent, which makes this approach flexible with respect to past approaches. In this paper, the use of this platform is illustrated for test optimization for the case of a fully differential amplifier. Test limits are set using a statistical circuit performance analysis that acounts for process deviations. Test metrics are estimated using this analysis. Specification-based tests are next optimized in terms of their capability of detecting catastrophic faults.
AB - This paper introduces a Computer-Aided-Test platform that has been developed for the evaluation of test techniques for analogue and mixed-signal circuits. The CAT platform, integrated in the Cadence Design Framework Environment, includes tools for fault simulation, test generation and test optimization for these types of circuits. Fault modeling and fault injection are simulator independent, which makes this approach flexible with respect to past approaches. In this paper, the use of this platform is illustrated for test optimization for the case of a fully differential amplifier. Test limits are set using a statistical circuit performance analysis that acounts for process deviations. Test metrics are estimated using this analysis. Specification-based tests are next optimized in terms of their capability of detecting catastrophic faults.
UR - https://www.scopus.com/pages/publications/46249108726
U2 - 10.1109/VLSISOC.2006.313254
DO - 10.1109/VLSISOC.2006.313254
M3 - Conference contribution
AN - SCOPUS:46249108726
SN - 3901882197
SN - 9783901882197
T3 - IFIP VLSI-SoIC 2006 - IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip
SP - 320
EP - 325
BT - IFIP VLSI-SoIC 2006 - IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip
T2 - IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip, VLSI-SoIC 2006
Y2 - 16 October 2006 through 18 October 2006
ER -