Abstract
As networks-on-chips (NoCs) are expected to provide the necessary scalable communication medium for future many-core systems-on-chips (SoCs) optimizing their resources is of great importance. What is really needed is an efficient NoC architecture with optimized resources that requires very little customization by the SoC developers. One of the most important area and power hungry resources is the NoC's buffers. In this work, a new Modified Fat Tree (MFT) NoC architecture with buffers engineered for maximum efficiency (performance versus area) is presented. Extensive simulations are used to show optimum buffer design/placement under different conditions of traffic types and NoC sizes.
| Original language | English |
|---|---|
| Article number | 1450105 |
| Journal | Journal of Circuits, Systems and Computers |
| Volume | 23 |
| Issue number | 7 |
| DOIs | |
| State | Published - Aug 2014 |
Bibliographical note
Funding Information:This work was supported by King Abdulaziz City for Science and Technology through the Science and Technology Unit at King Fahd University of Petroleum and Minerals (KFUPM) project no. 08-ELE-43-4 as part of the National Science, Technology and Innovation Plan. Also, facilities support by King Fahd University of Petroleum and Minerals is highly appreciated by the authors.
Keywords
- Chip multi-processors
- Many-core systems
- Networks-on-chip
- Systems-on-chip
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering