Abstract
A multistage self-routing permutation network is presented. This network is constructed from concentrators and digit-controlled 2x4 switches. A destination-tag routing scheme is used to realize any arbitrary permutation. The network has 0(log2 N) gate-delay and uses 0(N2) VLSI-area, where N is the number of inputs.1 Assuming packet-switching is used for message transmission, the delay and VLSI-area of the network are smaller than those of any self-routing permutation network presented to date.
| Original language | English |
|---|---|
| Pages (from-to) | 448-453 |
| Number of pages | 6 |
| Journal | IEEE Transactions on Computers |
| Volume | 44 |
| Issue number | 3 |
| DOIs | |
| State | Published - Mar 1995 |
| Externally published | Yes |
Bibliographical note
Funding Information:The authors thank A’ OrUc for his constmctive co“ents. This research was SupPofled in Pm by the U.S. office of Naval Research under contract NO. OOO14-904-1483a nd in part by the Innovative Science and Technology Office of the Strategic De-. fense Initiative Organization, and was administered through the of-. fice of Naval Research under contract No. 00014-88-k-0723.
ASJC Scopus subject areas
- Software
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics
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