Bounds on Net Delays for VLSI Circuits

Habib Youssef; Rung Bin Lin; Eugene Shragowitz

doi:10.1109/82.204129

Bounds on Net Delays for VLSI Circuits

Habib Youssef, Rung Bin Lin, Eugene Shragowitz

King Fahd University of Petroleum & Minerals

Research output: Contribution to journal › Article › peer-review

24 Scopus citations

Abstract

In the past, the dominant approach to solving timing problems in layout was based on sorting logical paths according to their criticality and assigning of different weights to nets. Timing-driven layout procedures used these weights to bias layout process. As an undesirable outcome, some noncritical paths became critical after layout. An alternative to the weight-based approach is development of delay bounds on all nets. In this paper, we discuss a formulation of this problem and suggest a new algorithm for its solution.

Original language	English
Pages (from-to)	815-824
Number of pages	10
Journal	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume	39
Issue number	11
DOIs	https://doi.org/10.1109/82.204129
State	Published - Nov 1992

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering

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10.1109/82.204129

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title = "Bounds on Net Delays for VLSI Circuits",

abstract = "In the past, the dominant approach to solving timing problems in layout was based on sorting logical paths according to their criticality and assigning of different weights to nets. Timing-driven layout procedures used these weights to bias layout process. As an undesirable outcome, some noncritical paths became critical after layout. An alternative to the weight-based approach is development of delay bounds on all nets. In this paper, we discuss a formulation of this problem and suggest a new algorithm for its solution.",

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AU - Lin, Rung Bin

AU - Shragowitz, Eugene

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AB - In the past, the dominant approach to solving timing problems in layout was based on sorting logical paths according to their criticality and assigning of different weights to nets. Timing-driven layout procedures used these weights to bias layout process. As an undesirable outcome, some noncritical paths became critical after layout. An alternative to the weight-based approach is development of delay bounds on all nets. In this paper, we discuss a formulation of this problem and suggest a new algorithm for its solution.

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M3 - Article

AN - SCOPUS:0026944819

SN - 1057-7130

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JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

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ER -

Bounds on Net Delays for VLSI Circuits

Abstract

ASJC Scopus subject areas

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