Automatic placement of micropipeline standard cells

A new algorithm for automated standard cell placement of asynchronous Micropipeline designs has been developed. The resulting placement solutions are targeted to meet all bundled-data timing constraints while providing efficient chip areas. The placement algorithm utilizes the simulated evolution iterative heuristic. The cost function is a weighted sum of an area factor and a timing factor. Results of five experimental circuits show that full routability with reasonably efficient areas are possible.