Asymmetrical Multilevel Inverter Topology with Reduced Number of Components

Marif Daula Siddique; Saad Mekhilef; Noraisyah Mohamed Shah; Adil Sarwar; Mudasir Ahmad Memon; Mehdi Seyedmahmoudian; Ben Horan; Alex Stojcevski; Koki Ogura; Muhyaddin Rawa; Hussain Bassi

doi:10.1109/PEDES.2018.8707663

Asymmetrical Multilevel Inverter Topology with Reduced Number of Components

Marif Daula Siddique
, Saad Mekhilef
, Noraisyah Mohamed Shah
, Adil Sarwar
, Mudasir Ahmad Memon
, Mehdi Seyedmahmoudian
, Ben Horan
, Alex Stojcevski
, Koki Ogura
, Muhyaddin Rawa
, Hussain Bassi

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

13 Scopus citations

Abstract

A new hybrid structure of multilevel inverter topology is recommended in this paper. It is designed with the aim of reducing the number of components with more number of levels at the output. Proposed topology uses three dc voltage sources along with 10 power semiconductor devices to achieve 13 levels at the output. A comparative study is given with other similar topologies which proves the lower number of components. In order to achieve good-quality output voltage, selective harmonic elimination technique is used with the elimination of lower order harmonics. Different simulation results have been provided to validate the proposed topology.

Original language	English
Title of host publication	Proceedings of 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538693155
DOIs	https://doi.org/10.1109/PEDES.2018.8707663
State	Published - 2 Jul 2018

Publication series

Name	Proceedings of 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2018

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

Asymmetrical
Hybrid
Multilevel inverter
Reduced switch count
Selective harmonic elimination (SHE)

ASJC Scopus subject areas

Electrical and Electronic Engineering
Energy Engineering and Power Technology
Fuel Technology

Access to Document

10.1109/PEDES.2018.8707663

Cite this

Siddique, M. D., Mekhilef, S., Shah, N. M., Sarwar, A., Memon, M. A., Seyedmahmoudian, M., Horan, B., Stojcevski, A., Ogura, K., Rawa, M., & Bassi, H. (2018). Asymmetrical Multilevel Inverter Topology with Reduced Number of Components. In Proceedings of 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2018 Article 8707663 (Proceedings of 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PEDES.2018.8707663

Siddique, Marif Daula ; Mekhilef, Saad ; Shah, Noraisyah Mohamed et al. / Asymmetrical Multilevel Inverter Topology with Reduced Number of Components. Proceedings of 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2018. Institute of Electrical and Electronics Engineers Inc., 2018. (Proceedings of 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2018).

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title = "Asymmetrical Multilevel Inverter Topology with Reduced Number of Components",

abstract = "A new hybrid structure of multilevel inverter topology is recommended in this paper. It is designed with the aim of reducing the number of components with more number of levels at the output. Proposed topology uses three dc voltage sources along with 10 power semiconductor devices to achieve 13 levels at the output. A comparative study is given with other similar topologies which proves the lower number of components. In order to achieve good-quality output voltage, selective harmonic elimination technique is used with the elimination of lower order harmonics. Different simulation results have been provided to validate the proposed topology.",

keywords = "Asymmetrical, Hybrid, Multilevel inverter, Reduced switch count, Selective harmonic elimination (SHE)",

author = "Siddique, \{Marif Daula\} and Saad Mekhilef and Shah, \{Noraisyah Mohamed\} and Adil Sarwar and Memon, \{Mudasir Ahmad\} and Mehdi Seyedmahmoudian and Ben Horan and Alex Stojcevski and Koki Ogura and Muhyaddin Rawa and Hussain Bassi",

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doi = "10.1109/PEDES.2018.8707663",

language = "English",

series = "Proceedings of 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2018",

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Siddique, MD, Mekhilef, S, Shah, NM, Sarwar, A, Memon, MA, Seyedmahmoudian, M, Horan, B, Stojcevski, A, Ogura, K, Rawa, M & Bassi, H 2018, Asymmetrical Multilevel Inverter Topology with Reduced Number of Components. in Proceedings of 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2018., 8707663, Proceedings of 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2018, Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1109/PEDES.2018.8707663

Asymmetrical Multilevel Inverter Topology with Reduced Number of Components. / Siddique, Marif Daula; Mekhilef, Saad; Shah, Noraisyah Mohamed et al.
Proceedings of 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2018. Institute of Electrical and Electronics Engineers Inc., 2018. 8707663 (Proceedings of 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Shah, Noraisyah Mohamed

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AU - Memon, Mudasir Ahmad

AU - Seyedmahmoudian, Mehdi

AU - Horan, Ben

AU - Stojcevski, Alex

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N2 - A new hybrid structure of multilevel inverter topology is recommended in this paper. It is designed with the aim of reducing the number of components with more number of levels at the output. Proposed topology uses three dc voltage sources along with 10 power semiconductor devices to achieve 13 levels at the output. A comparative study is given with other similar topologies which proves the lower number of components. In order to achieve good-quality output voltage, selective harmonic elimination technique is used with the elimination of lower order harmonics. Different simulation results have been provided to validate the proposed topology.

AB - A new hybrid structure of multilevel inverter topology is recommended in this paper. It is designed with the aim of reducing the number of components with more number of levels at the output. Proposed topology uses three dc voltage sources along with 10 power semiconductor devices to achieve 13 levels at the output. A comparative study is given with other similar topologies which proves the lower number of components. In order to achieve good-quality output voltage, selective harmonic elimination technique is used with the elimination of lower order harmonics. Different simulation results have been provided to validate the proposed topology.

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BT - Proceedings of 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2018

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Siddique MD, Mekhilef S, Shah NM, Sarwar A, Memon MA, Seyedmahmoudian M et al. Asymmetrical Multilevel Inverter Topology with Reduced Number of Components. In Proceedings of 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2018. Institute of Electrical and Electronics Engineers Inc. 2018. 8707663. (Proceedings of 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2018). doi: 10.1109/PEDES.2018.8707663

Asymmetrical Multilevel Inverter Topology with Reduced Number of Components

Abstract

Publication series

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this